Test platform for fault tolerant systems design properties verification

Abstract

In this paper, a methodology for fault tolerant systems design properties verification is presented together with recovery technique for a fault tolerant system after soft errors occurrence in a SRAM-based FPGA. First, the principles of test platform based on an external SEU injector are presented; all components of test platform and their role during SEU simulation are described. Then, a recovery technique based on the generic partial dynamic reconfiguration controller implemented inside an FPGA is presented. The controller is used for the identification of a faulty module in the fault tolerant system, reconfiguration of this module through ICAP interface and synchronization of the module after reconfiguration process with other modules in the system. The controller can be used for the identification of permanent faults in the FPGA structure as well. The first experiments with a test platform and reconfiguration controller are discussed in this paper.