Complementary edge alignment and digital output signal speed-up CMOS positive feedback latches

Abstract

The paper elaborates on a kind of positive feedback latch that is not used as a memory element but rather for purposes of complementary signal edge alignment and digital output signal speed-up. The theoretical background behind positive exponential rise latches is presented in detail. The proposed latch is fully differential, fully complementary and perfectly symmetrical. It is structurally composed through comparisons with the set-reset (SR) latch and is implemented in CMOS technology. Simulation results show that the proposed circuit improves the state switching ability thus relaxing the design constraints connected to the latch interface. The latch, hence allows larger optimization space which leads to a better design.