基于90纳米CMOS技术的1.575 GHz低功耗均衡器设计

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) Pub Date : 2012-04-18 DOI:10.1109/DDECS.2012.6219067

Jacek Gradzki

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引用次数: 0

摘要

本文提出了一种低功率平衡器的设计方法。它针对1.575 GHz进行了优化，采用90 nm UMC CMOS技术设计。在1.2 V电源电压下，电流消耗仅为0.44 mA。仿真结果表明，增益和相位不平衡分别为0.08 dB和0.045°。该电路的单端功率增益为2.2 dB。一个特殊的尺寸匹配已经做了，以尽量减少电路的敏感性变化的制造过程。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Low power balun Design for 1.575 GHz in 90 nm CMOS rechnology

In this paper low power balun design is presented. It is optimized for 1.575 GHz and designed in 90 nm UMC CMOS technology. Current consumption is only 0.44 mA under 1.2 V supply voltage. The simulation shows that gain and phase imbalance are equal to 0.08 dB and 0.045°, respectively. Single-ended power gain of this circuit is 2.2 dB. A special dimension matching has been made to minimize circuit susceptibility to variation of the manufacturing process.

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2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)

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