VHDLVisualizer: HDL model visualization with simulation-based verification

Abstract

The usage of the HDLs (Hardware Description Languages) in the present digital system development process is indispensable. Although, their great contribution is undeniable, they also bring about several disadvantages. The textual form of an HDL model is less illustrative for a human being than schematic representation of its structure. Moreover, simulation of such models is most commonly displayed in a waveform representation, even though sufficient for verification, it is hard-to-identify design errors. The paper presents a tool for supporting both, the model structure visualization and the simulation results in the visualized structure display.