Effective RT-level software-based self-testing of embedded processor cores

Abstract

Embedded processors are often used in systems that are both safety-critical and long-living. Therefore testing of these devices is critical not only after production, but also in the field. Due to the limited accessibility of embedded processors, testing of such systems is a major challenge in terms of ultra-deep submicron issues. Scan based testing methods cannot be applied to embedded processor cores which cannot be modified to meet the design requirements for scan insertion. From the other side, generating test vectors for these high gate count devices is a major task. This paper presents a high level, component-oriented software-based self-testing method which achieves a high stuck-at-fault coverage for an embedded processor core. The method requires no DFT or changing the processor architecture. The proposed method is high level in the sense that it is based on the knowledge of the Instruction Set Architecture (ISA) and Register Transfer Level (RTL) description of the processor. The method is well suited for meeting the challenges of testing SoCs which contain embedded processor cores. Our methodology is superior in terms of test quality in such a way that significantly increases fault coverage and reduces test time. The proposed method outperforms all existing method in terms of fault coverage.