A 512 kb SRAM in 65nm CMOS with divided bitline and novel two-stage sensing technique

Abstract

This paper focuses on high speed embedded SRAM design, especially on novel circuit technique to improve SRAM access time. A new two-stage sensing scheme which is able to reduce long interconnection metal line delay by transferring differential signals with half swing amplitude has been proposed. Post-layout simulation results show that the long distance signal transmission time has been decreased by 45%. Chip measurement shows the access time has been decreased by 23% at the expense of little area penalty (1.3%) and some read power penalty (about 16%) mainly caused by 2nd-stage sense amplifiers.