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[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium最新文献

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Prober for highly integrated multichip modules 探头用于高度集成的多芯片模块
[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1991-09-16 DOI: 10.1109/IEMT.1991.279831
T. Sakata, K. Numata
{"title":"Prober for highly integrated multichip modules","authors":"T. Sakata, K. Numata","doi":"10.1109/IEMT.1991.279831","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279831","url":null,"abstract":"A prober for function test of LSIs on multichip modules of Hitachi's newest mainframe M-880 series has been developed. The test is performed by making contact between probes and metallic pads on the module substrate. A visual feedback positioning system is employed to position a probe head, in which the probes are installed, precisely on the module. The prober has four TV cameras to compensate for the location error of module mounting, the location error of probe head holding, and thermal deformation of the module and the prober. Control values of the positioning table, which carries the probe head to a testing point, are calculated by some coordinate transformations with the use of the TV cameras' outputs and position data measured in the fabrication process of the module and the probe head.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"31 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121993375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Surface mounting of very fine pitch components: a new challenge 极细螺距部件的表面安装:一个新的挑战
[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1991-09-16 DOI: 10.1109/IEMT.1991.279768
J. Joly, X. Saint Martin
{"title":"Surface mounting of very fine pitch components: a new challenge","authors":"J. Joly, X. Saint Martin","doi":"10.1109/IEMT.1991.279768","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279768","url":null,"abstract":"Based on their experience in developing and using 16 and 12.5 mils peripheral pitch custom compact single chip packages, the authors analyze the evolution and today's limits of package and board technologies and assembly techniques, with emphasis on manufacturability. The authors present their manufacturing approach and quality and reliability results when using 16 and 12.5 mils peripheral ceramic leaded packages. A detailed analysis of packaging processes and limitations is performed for high pin count ceramic and plastic packages. Competitive packaging methods, pin grid arrays, land grid arrays, and tape automated bonding are compared, and trends for the future are analyzed.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"239 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116468758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Statistically designed polyimide coating process for TAB bumping 统计设计聚酰亚胺涂层工艺的标签碰撞
[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1991-09-16 DOI: 10.1109/IEMT.1991.279737
N. Gayeli, L. Ellis, J. Jasper
{"title":"Statistically designed polyimide coating process for TAB bumping","authors":"N. Gayeli, L. Ellis, J. Jasper","doi":"10.1109/IEMT.1991.279737","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279737","url":null,"abstract":"Design of experiments and statistical data analysis were used to develop a wafer coating process for straight wall bumping of 6\" wafers for TAB (tape automated bonding). The effect of important parameters and their interactions on polyimide coat thickness, uniformity, and quality were identified, and models were developed. Using the results of the experiments, a dynamic coating process was developed which provided well-controlled polyimide coating for the straight wall bumping process. Subsequent results showed excellent correlation between measured values and predicted values from models.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116163372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Method for semiconductor process optimization using functional representations of spatial variations and selectivity 利用空间变化和选择性的功能表示进行半导体工艺优化的方法
[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1991-09-16 DOI: 10.1109/IEMT.1991.279760
P. K. Mozumder, L. Loewenstein
{"title":"Method for semiconductor process optimization using functional representations of spatial variations and selectivity","authors":"P. K. Mozumder, L. Loewenstein","doi":"10.1109/IEMT.1991.279760","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279760","url":null,"abstract":"The authors present a methodology for determining the optimal equipment settings for a processing step based on experiment designs and model-based optimization. The proposed method for semiconductor process optimization uses two-layered models. The first layer involves creating a spatial model-one for each film of interest-of the etch results. The second layer maps the coefficients of the spatial models to equipment settings. All this is done before any optimization scheme is employed. The process engineer then may optimize the etch process by maximizing coefficients which contribute to the desired maximum etch rate, while minimizing coefficients which contribute to nonuniformity. He also may minimize coefficients which represent undesired etches, and thus obtain etch selectivity. The results of a study of a plasma-assisted silicon nitride etch step are presented.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127098213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
The key sputter deposition step in TAB wafer bump processing: optimizing TiW adhesion and diffusion barrier properties TAB晶圆凹凸加工中关键的溅射沉积步骤:优化TiW的粘附和扩散阻挡性能
[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1991-09-16 DOI: 10.1109/IEMT.1991.279736
J. Traut
{"title":"The key sputter deposition step in TAB wafer bump processing: optimizing TiW adhesion and diffusion barrier properties","authors":"J. Traut","doi":"10.1109/IEMT.1991.279736","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279736","url":null,"abstract":"Sputter deposition is used in tape automated bonding (TAB) as the first step of wafer processing in order to plate gold bumps at the die pads. The adhesion and barrier properties of TiW films are investigated here. Adhesion is critical for TAB as bond strengths are touted to be 2-x to 3-x that of wire bonding. Barrier integrity is important to enhance the hermetic seal properties again touted with TAB. TiW film thicknesses, the structure of TiW and TiWN layering, and deposition characteristics are described in optimizing the TAB sputter deposition process.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114407093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multichip modules fabrication, a transition from prototypes to production 多芯片模块制造，从原型到生产的过渡
[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1991-09-16 DOI: 10.1109/IEMT.1991.279789
J. Reche
{"title":"Multichip modules fabrication, a transition from prototypes to production","authors":"J. Reche","doi":"10.1109/IEMT.1991.279789","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279789","url":null,"abstract":"The author presents an overview of the rationale behind a pilot facility for manufacturing multichip modules, using a high density multilayer interconnect (HDMI) technology. Although HDMI multichip module fabrication equipment and techniques are somewhat related to semiconductor fabrication, there are significant differences which are due to the size of finished parts and to the materials used in the fabrication of MCMs. Past its initial learning curve, minimized costs for second level interconnection are expected from the HDMI technology, because of its optimized geometries compared to other potential second level interconnect technologies. The recently completed pilot facility is to provide data in preparation for the construction of other future large facilities capable of producing parts in large volume, at low cost, for the commercial market. It is pointed out that in order to compete in the world market and to keep a leading edge over competitors, older labor intensive techniques of operating semiconductor plants must be replaced by aggressive automatization.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129273915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Laser created silicon vias for stacking dies in MCMs 激光创造了硅孔，用于在mcm中堆叠模具
[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1991-09-16 DOI: 10.1109/IEMT.1991.279791
R. Lee, D. Whittaker
{"title":"Laser created silicon vias for stacking dies in MCMs","authors":"R. Lee, D. Whittaker","doi":"10.1109/IEMT.1991.279791","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279791","url":null,"abstract":"The stacking of silicon devices is gaining some interest as it will allow even greater densities over current multichip module (MCM) approaches. One type of approach being tried in the industry is interconnecting stacked dies by routing their metal lines to the edge of the die and then strapping the appropriate lines from each die together. An approach being pursued by the Center for Microelectronics Research (CMR) at the University of South Florida is the creation of silicon interconnect vias for communication through the active chip or wafer. Vias of 1 to 2 mil diameters have been successfully created by laser ablation of silicon. Studies are currently in progress to determine the effect such via creation has on nearby active devices. A test vehicle containing transistors and capacitors of various geometries is being employed for the purpose of measuring any detriment that the laser drilling has when vias are created. Data are presented on whether any changes have been measured in various parameters, such as subthreshold voltages and current leakage. Scanning electron micrographs are shown, and progress to date on the methodology employed for metallizing the side walls of the vias is discussed.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117217099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Highly manufacturable multi-layered ceramic surface mounted package 高度可制造的多层陶瓷表面安装封装
[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1991-09-16 DOI: 10.1109/IEMT.1991.279830
F.F. Cappo, J. Milliken, J. Mosley
{"title":"Highly manufacturable multi-layered ceramic surface mounted package","authors":"F.F. Cappo, J. Milliken, J. Mosley","doi":"10.1109/IEMT.1991.279830","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279830","url":null,"abstract":"A surface mount package was designed in 1983 to satisfy a multi-chip cost-performance market requirement where a large number of components can be replaced with a few integrated devices in a single package. It was decided to use the IBM multi-layer ceramic (MLC) technology for the carrier substrate because of proven reliability, volume manufacturing capacity, multi-chip capability, wiring flexibility, and performance. Second, it was decided to use a specially designed surface-mount technology (SMT) interconnection to the card instead of the industry standard SMT or pin in hole because of I/O density, cost, and performance. The SMT interconnection was refined through theoretical and empirical investigation along with the low cost, high manufacturability requirement. The result was a high melting point Sn/Pb ball placed in a 0.50\" grid array attached to the substrate and card using eutectic solder. Design concepts to aid in manufacturing are discussed together with the manufacturing/process design, and a typical example of this packaging technology is presented.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116271565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A statistical method to integrate manufacturing tolerance in high-speed digital circuit design 高速数字电路设计中集成制造公差的统计方法
[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1991-09-16 DOI: 10.1109/IEMT.1991.279823
N. Goel, K. Kalaichelvan, B. Bleuer
{"title":"A statistical method to integrate manufacturing tolerance in high-speed digital circuit design","authors":"N. Goel, K. Kalaichelvan, B. Bleuer","doi":"10.1109/IEMT.1991.279823","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279823","url":null,"abstract":"The authors outline a computationally efficient statistical method to design high-speed digital circuits, taking into account the manufacturing tolerance of interconnects. The proposed method can be used in the design of high-density printed circuit packs and multi-chip modules (MCMs). It can also be used to bring the aspects of manufacturability into the early stage of the design to minimize the cycle time between design and the final product. The design process presented here uses Monte Carlo analysis along with stochastic approximation to optimize the cost per satisfactory circuit. A relationship is established between the electrical requirements and the manufacturing tolerance of interconnects. Manufacturability signature profiles are presented for various interconnect configurations such as microstrip and buried microstrip. Finally, the simulation results are verified experimentally for the design of MCMs and are found to be in good agreement.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114382569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Packaging alternatives for high lead count, fine pitch, surface mount technology 封装替代高引脚数，细间距，表面贴装技术
[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1991-09-16 DOI: 10.1109/IEMT.1991.279773
R. Chroneos, D. Mallik, S. Prough
{"title":"Packaging alternatives for high lead count, fine pitch, surface mount technology","authors":"R. Chroneos, D. Mallik, S. Prough","doi":"10.1109/IEMT.1991.279773","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279773","url":null,"abstract":"It is noted that fine pitch SMT (surface mount technology) components potentially offer substantial benefits for cost, performance, and miniaturization in assembly of high integration, high lead count ICs in portable electronic systems. However, several issues involving component handling, solder process, rework, and reliability concerns must first be overcome. It is noted that a variety of packaging alternatives exist today for surface mount high leadcount components. Any choice must address these surface mount issues as well as the requirements of next-generation highly integrated, high-performance IC devices. Details of various packaging alternatives are discussed.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114840286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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