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[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium最新文献

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Quality Vision 2000 (quality management system) 质量愿景2000(质量管理体系)
[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1991-09-16 DOI: 10.1109/IEMT.1991.279820
S. Rabe, J. Mann
{"title":"Quality Vision 2000 (quality management system)","authors":"S. Rabe, J. Mann","doi":"10.1109/IEMT.1991.279820","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279820","url":null,"abstract":"The authors describe Quality Vision 2000, a package of management systems improvements intended to build to total quality environment. They discuss quality elements and systems used during the 1970s and 1980s, and the results achieved. These include PPM, statistical process control, Cpk, designed experiments, and quality circles. It is noted that involvement with customers including technical seminars, design reviews, Beta sight testing, surveys, and overall perception will be a key to meeting the objectives of Quality Vision 2000. During the 1990s existing elements will be strengthened and new elements will be added to meet the objective of total customer satisfaction. Key elements, methods, and measurements for Quality Vision 2000 are presented.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132475962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Thermal design for high-speed, high-density multi-chip module 热设计为高速、高密度多芯片模块
[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1991-09-16 DOI: 10.1109/IEMT.1991.279792
T. Handa, S. Iida, J. Utsunomiya
{"title":"Thermal design for high-speed, high-density multi-chip module","authors":"T. Handa, S. Iida, J. Utsunomiya","doi":"10.1109/IEMT.1991.279792","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279792","url":null,"abstract":"Examines the boundary conditions of models for finite element analysis of the thermal design of high-speed, high-density multi-chip modules, principally the thermal via and heat sink, and investigates means of improving the accuracy of heat transfer analysis simulation. It is concluded that, in evaluating the effectiveness of thermal vias in heat loss, simulation can yield results close to observed values by considering the substrate a compound material with a uniform thermal and conductivity coefficient determined by the ratio of thermal via cross section area to substrate area. A thermal via area ratio of 10% is satisfactory both from the standpoint of manufacturing and for effectiveness in decreasing thermal resistance. Also, in the model considered the heat transfer coefficient of the heat sink can be determined by using their speeds and comparison with observed results.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134236642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A software tool for technology tradeoff evaluation in multichip packaging 多芯片封装技术权衡评估的软件工具
[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1991-09-16 DOI: 10.1109/IEMT.1991.279809
P. Sandborn
{"title":"A software tool for technology tradeoff evaluation in multichip packaging","authors":"P. Sandborn","doi":"10.1109/IEMT.1991.279809","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279809","url":null,"abstract":"A software tool for evaluating performance tradeoffs in multichip packaging is described. The tool enhances the manufacturability and decreases the design risk associated with the selection of packaging technologies for integrated circuits. Geometric, electrical, thermal, and manufacturing metrics can be estimated using the tool. The tool allows technologies to be changed and design rules to be modified using a what if approach. The role of technology tradeoff analysis in multichip system design and system compiler concepts are discussed, and implementation details of the present tool are described. A design example of a RISC processor module is presented, and the use of the tool for assessing mixed technology systems is demonstrated.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124321807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Multichip modules fabrication, a transition from prototypes to production 多芯片模块制造，从原型到生产的过渡
[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1991-09-16 DOI: 10.1109/IEMT.1991.279789
J. Reche
{"title":"Multichip modules fabrication, a transition from prototypes to production","authors":"J. Reche","doi":"10.1109/IEMT.1991.279789","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279789","url":null,"abstract":"The author presents an overview of the rationale behind a pilot facility for manufacturing multichip modules, using a high density multilayer interconnect (HDMI) technology. Although HDMI multichip module fabrication equipment and techniques are somewhat related to semiconductor fabrication, there are significant differences which are due to the size of finished parts and to the materials used in the fabrication of MCMs. Past its initial learning curve, minimized costs for second level interconnection are expected from the HDMI technology, because of its optimized geometries compared to other potential second level interconnect technologies. The recently completed pilot facility is to provide data in preparation for the construction of other future large facilities capable of producing parts in large volume, at low cost, for the commercial market. It is pointed out that in order to compete in the world market and to keep a leading edge over competitors, older labor intensive techniques of operating semiconductor plants must be replaced by aggressive automatization.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129273915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Laser created silicon vias for stacking dies in MCMs 激光创造了硅孔，用于在mcm中堆叠模具
[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1991-09-16 DOI: 10.1109/IEMT.1991.279791
R. Lee, D. Whittaker
{"title":"Laser created silicon vias for stacking dies in MCMs","authors":"R. Lee, D. Whittaker","doi":"10.1109/IEMT.1991.279791","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279791","url":null,"abstract":"The stacking of silicon devices is gaining some interest as it will allow even greater densities over current multichip module (MCM) approaches. One type of approach being tried in the industry is interconnecting stacked dies by routing their metal lines to the edge of the die and then strapping the appropriate lines from each die together. An approach being pursued by the Center for Microelectronics Research (CMR) at the University of South Florida is the creation of silicon interconnect vias for communication through the active chip or wafer. Vias of 1 to 2 mil diameters have been successfully created by laser ablation of silicon. Studies are currently in progress to determine the effect such via creation has on nearby active devices. A test vehicle containing transistors and capacitors of various geometries is being employed for the purpose of measuring any detriment that the laser drilling has when vias are created. Data are presented on whether any changes have been measured in various parameters, such as subthreshold voltages and current leakage. Scanning electron micrographs are shown, and progress to date on the methodology employed for metallizing the side walls of the vias is discussed.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117217099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Highly manufacturable multi-layered ceramic surface mounted package 高度可制造的多层陶瓷表面安装封装
[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1991-09-16 DOI: 10.1109/IEMT.1991.279830
F.F. Cappo, J. Milliken, J. Mosley
{"title":"Highly manufacturable multi-layered ceramic surface mounted package","authors":"F.F. Cappo, J. Milliken, J. Mosley","doi":"10.1109/IEMT.1991.279830","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279830","url":null,"abstract":"A surface mount package was designed in 1983 to satisfy a multi-chip cost-performance market requirement where a large number of components can be replaced with a few integrated devices in a single package. It was decided to use the IBM multi-layer ceramic (MLC) technology for the carrier substrate because of proven reliability, volume manufacturing capacity, multi-chip capability, wiring flexibility, and performance. Second, it was decided to use a specially designed surface-mount technology (SMT) interconnection to the card instead of the industry standard SMT or pin in hole because of I/O density, cost, and performance. The SMT interconnection was refined through theoretical and empirical investigation along with the low cost, high manufacturability requirement. The result was a high melting point Sn/Pb ball placed in a 0.50\" grid array attached to the substrate and card using eutectic solder. Design concepts to aid in manufacturing are discussed together with the manufacturing/process design, and a typical example of this packaging technology is presented.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116271565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A statistical method to integrate manufacturing tolerance in high-speed digital circuit design 高速数字电路设计中集成制造公差的统计方法
[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1991-09-16 DOI: 10.1109/IEMT.1991.279823
N. Goel, K. Kalaichelvan, B. Bleuer
{"title":"A statistical method to integrate manufacturing tolerance in high-speed digital circuit design","authors":"N. Goel, K. Kalaichelvan, B. Bleuer","doi":"10.1109/IEMT.1991.279823","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279823","url":null,"abstract":"The authors outline a computationally efficient statistical method to design high-speed digital circuits, taking into account the manufacturing tolerance of interconnects. The proposed method can be used in the design of high-density printed circuit packs and multi-chip modules (MCMs). It can also be used to bring the aspects of manufacturability into the early stage of the design to minimize the cycle time between design and the final product. The design process presented here uses Monte Carlo analysis along with stochastic approximation to optimize the cost per satisfactory circuit. A relationship is established between the electrical requirements and the manufacturing tolerance of interconnects. Manufacturability signature profiles are presented for various interconnect configurations such as microstrip and buried microstrip. Finally, the simulation results are verified experimentally for the design of MCMs and are found to be in good agreement.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114382569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Packaging alternatives for high lead count, fine pitch, surface mount technology 封装替代高引脚数，细间距，表面贴装技术
[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1991-09-16 DOI: 10.1109/IEMT.1991.279773
R. Chroneos, D. Mallik, S. Prough
{"title":"Packaging alternatives for high lead count, fine pitch, surface mount technology","authors":"R. Chroneos, D. Mallik, S. Prough","doi":"10.1109/IEMT.1991.279773","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279773","url":null,"abstract":"It is noted that fine pitch SMT (surface mount technology) components potentially offer substantial benefits for cost, performance, and miniaturization in assembly of high integration, high lead count ICs in portable electronic systems. However, several issues involving component handling, solder process, rework, and reliability concerns must first be overcome. It is noted that a variety of packaging alternatives exist today for surface mount high leadcount components. Any choice must address these surface mount issues as well as the requirements of next-generation highly integrated, high-performance IC devices. Details of various packaging alternatives are discussed.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114840286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Testability challenges to achieve zero defect goal in MCM manufacturing 在MCM制造中实现零缺陷目标的可测试性挑战
[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1991-09-16 DOI: 10.1109/IEMT.1991.279827
D. McQueeney, T. Zittritsch
{"title":"Testability challenges to achieve zero defect goal in MCM manufacturing","authors":"D. McQueeney, T. Zittritsch","doi":"10.1109/IEMT.1991.279827","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279827","url":null,"abstract":"Discusses some approaches to chip test and MCM (multi-chip module) assembly, and describes a module designed for CMOS logic, including details of its chip attach technology, test, and burn-in strategy. It is concluded that test procedures can be more easily implemented if the chips are designed for an MCM environment. Two significant challenges are the use on an MCM of chips whose design did not consider MCM test issues, and modules made up of chips from different manufacturers.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126896309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Using fuzzy mathematics to detect dimple defects of polished wafer surface 利用模糊数学方法检测抛光晶圆表面的凹陷缺陷
[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium Pub Date : 1991-09-16 DOI: 10.1109/IEMT.1991.279774
J.C. Lin, H. Li, Y. Ji
{"title":"Using fuzzy mathematics to detect dimple defects of polished wafer surface","authors":"J.C. Lin, H. Li, Y. Ji","doi":"10.1109/IEMT.1991.279774","DOIUrl":"https://doi.org/10.1109/IEMT.1991.279774","url":null,"abstract":"Using the concept of fuzzy mathematics, the authors developed an automated visual inspection system to detect dimple defects of polished wafer surfaces. The algorithm consists of two major processing phases. At the first phase, pre-processing is performed to eliminate noise and to reduce the number of potential candidates of dimple defects. At the second phase, four pattern features are defined based on the consideration of scale-, position-, and orientation-invariant. A fuzzy membership function is utilized to cope with the wide range of shape variations of the dimple defects. A decision-making mechanism is based on the value of the membership function which describes the pattern's closeness to a dimple. The attractive features of the system include the fact that the algorithm is distortion-invariant. Experimental results are presented.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125181383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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