{"title":"多芯片封装技术权衡评估的软件工具","authors":"P. Sandborn","doi":"10.1109/IEMT.1991.279809","DOIUrl":null,"url":null,"abstract":"A software tool for evaluating performance tradeoffs in multichip packaging is described. The tool enhances the manufacturability and decreases the design risk associated with the selection of packaging technologies for integrated circuits. Geometric, electrical, thermal, and manufacturing metrics can be estimated using the tool. The tool allows technologies to be changed and design rules to be modified using a what if approach. The role of technology tradeoff analysis in multichip system design and system compiler concepts are discussed, and implementation details of the present tool are described. A design example of a RISC processor module is presented, and the use of the tool for assessing mixed technology systems is demonstrated.<<ETX>>","PeriodicalId":127257,"journal":{"name":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1991-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A software tool for technology tradeoff evaluation in multichip packaging\",\"authors\":\"P. Sandborn\",\"doi\":\"10.1109/IEMT.1991.279809\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A software tool for evaluating performance tradeoffs in multichip packaging is described. The tool enhances the manufacturability and decreases the design risk associated with the selection of packaging technologies for integrated circuits. Geometric, electrical, thermal, and manufacturing metrics can be estimated using the tool. The tool allows technologies to be changed and design rules to be modified using a what if approach. The role of technology tradeoff analysis in multichip system design and system compiler concepts are discussed, and implementation details of the present tool are described. A design example of a RISC processor module is presented, and the use of the tool for assessing mixed technology systems is demonstrated.<<ETX>>\",\"PeriodicalId\":127257,\"journal\":{\"name\":\"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1991-09-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEMT.1991.279809\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1991 Proceedings] Eleventh IEEE/CHMT International Electronics Manufacturing Technology Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEMT.1991.279809","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A software tool for technology tradeoff evaluation in multichip packaging
A software tool for evaluating performance tradeoffs in multichip packaging is described. The tool enhances the manufacturability and decreases the design risk associated with the selection of packaging technologies for integrated circuits. Geometric, electrical, thermal, and manufacturing metrics can be estimated using the tool. The tool allows technologies to be changed and design rules to be modified using a what if approach. The role of technology tradeoff analysis in multichip system design and system compiler concepts are discussed, and implementation details of the present tool are described. A design example of a RISC processor module is presented, and the use of the tool for assessing mixed technology systems is demonstrated.<>
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