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Proceedings Ninth Great Lakes Symposium on VLSI最新文献

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Formal verification of tree-structured carry-lookahead adders 树形进位加法器的形式化验证
Proceedings Ninth Great Lakes Symposium on VLSI Pub Date : 1999-03-04 DOI: 10.1109/GLSV.1999.757419
Sae Hwan Kim, Shiu-Kai Chin
{"title":"Formal verification of tree-structured carry-lookahead adders","authors":"Sae Hwan Kim, Shiu-Kai Chin","doi":"10.1109/GLSV.1999.757419","DOIUrl":"https://doi.org/10.1109/GLSV.1999.757419","url":null,"abstract":"Quad trees-trees with four branches, are used to abstractly describe tree-structured carry-lookahead adders using 4-bit components. The specification and implementation descriptions are parametrized and tree-structured adders having arbitrarily large inputs and outputs are described. The descriptions are formally verified using the HOL theorem power.","PeriodicalId":127222,"journal":{"name":"Proceedings Ninth Great Lakes Symposium on VLSI","volume":"233 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121029835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Methodology of logic synthesis for implementation using heterogeneous LUT FPGAs 使用异构LUT fpga实现的逻辑综合方法学
Proceedings Ninth Great Lakes Symposium on VLSI Pub Date : 1999-03-04 DOI: 10.1109/GLSV.1999.757424
I. Lemberski
{"title":"Methodology of logic synthesis for implementation using heterogeneous LUT FPGAs","authors":"I. Lemberski","doi":"10.1109/GLSV.1999.757424","DOIUrl":"https://doi.org/10.1109/GLSV.1999.757424","url":null,"abstract":"Logic synthesis method for heterogeneous LUT FPGAs implementation is proposed As all example, XILINX4000 architecture is considered. The method takes XILINX4000 architectural features (heterogeneous LUTs of 3 and 4 inputs) into account and includes two step decomposition. In the first step, two-level logic representation is transformed into a graph of at most 4 fanin nodes (after this step, each node can be mapped onto 4 input LUT). In the second step, selected 4 fanin nodes are re-decomposed into 3 fanin nodes to ensure mapping onto 3 input LUTs. Re-decomposition task is formulated as substituting node two fanins for exactly one fanin.","PeriodicalId":127222,"journal":{"name":"Proceedings Ninth Great Lakes Symposium on VLSI","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116434879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Congestion mitigation during placement 安置期间纾缓挤塞
Proceedings Ninth Great Lakes Symposium on VLSI Pub Date : 1999-03-04 DOI: 10.1109/GLSV.1999.757417
K. Chakraborty, Natesan Venkateswaran
{"title":"Congestion mitigation during placement","authors":"K. Chakraborty, Natesan Venkateswaran","doi":"10.1109/GLSV.1999.757417","DOIUrl":"https://doi.org/10.1109/GLSV.1999.757417","url":null,"abstract":"High post-placement congestion in complex ASICs and microprocessors may pose severe constraints on the wiring resources, thereby causing wireability, timing and noise problems. Linear wirelength-based mincut partitioning algorithms have some built-in advantages for reducing congestion. We present a mathematical model of congestion and experimentally investigate various congestion mitigation techniques used in conjunction with linear wirelength-based placement. The experimental results validate our congestion model. Our placement tool, CPlace(C), is a clustering-based mincut partitioner that optimizes a linear wirelength objective.","PeriodicalId":127222,"journal":{"name":"Proceedings Ninth Great Lakes Symposium on VLSI","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122388431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design recovery for incomplete combinational logic 不完全组合逻辑的设计恢复
Proceedings Ninth Great Lakes Symposium on VLSI Pub Date : 1999-03-04 DOI: 10.1109/GLSV.1999.757406
T. Doom, A. S. Wojcik, M. Chung
{"title":"Design recovery for incomplete combinational logic","authors":"T. Doom, A. S. Wojcik, M. Chung","doi":"10.1109/GLSV.1999.757406","DOIUrl":"https://doi.org/10.1109/GLSV.1999.757406","url":null,"abstract":"Motivated by the problem of reengineering legacy digital circuits for which design information is missing or incomplete, this paper presents a new technique for representing the relationships among the internal components of a combinational circuit. This technique proves to be a powerful tool for redesign, capable of representing internal Boolean relationships in a fully or partially specified multiple-output combinational circuit with a single data structure.","PeriodicalId":127222,"journal":{"name":"Proceedings Ninth Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129897645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Blending symbolic matrix and dimensional numerical simulation methodology for mechatronics systems 机电一体化系统符号矩阵与量纲数值模拟的混合方法
Proceedings Ninth Great Lakes Symposium on VLSI Pub Date : 1999-03-04 DOI: 10.1109/GLSV.1999.757431
R. Ewing
{"title":"Blending symbolic matrix and dimensional numerical simulation methodology for mechatronics systems","authors":"R. Ewing","doi":"10.1109/GLSV.1999.757431","DOIUrl":"https://doi.org/10.1109/GLSV.1999.757431","url":null,"abstract":"The methodology for the integration of design domains towards the purpose of controlling dynamic mechatronics systems is the current challenge of the modern engineer. Scaling issues for both the mechanical and electrical parameters are critical to the successful design and implementation of a mechatronic system. In approaching the scaling design methodology for future submicron fabrication, new disciplines of symbolic matrix techniques and dimensional analysis must be developed and applied in the design of these mechatronics systems. This paper presents both an overview of the techniques and insight using computer aided design packages for the blending of symbolic matrix techniques using the admittance matrix created by SPICE and dimensional analysis using Buckingham's /spl Pi/ parameters.","PeriodicalId":127222,"journal":{"name":"Proceedings Ninth Great Lakes Symposium on VLSI","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128027074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
On path delay fault testing of multiplexer-based shifters 基于多路复用器的移位器路径延迟故障测试
Proceedings Ninth Great Lakes Symposium on VLSI Pub Date : 1999-03-04 DOI: 10.1080/00207210110058139
H. T. Vergos, D. Nikolos, Y. Tsiatouhas, T. Haniotakis, M. Nicolaidis
{"title":"On path delay fault testing of multiplexer-based shifters","authors":"H. T. Vergos, D. Nikolos, Y. Tsiatouhas, T. Haniotakis, M. Nicolaidis","doi":"10.1080/00207210110058139","DOIUrl":"https://doi.org/10.1080/00207210110058139","url":null,"abstract":"In this paper we present a method for path delay fault testing of multiplexer-based shifters. We show that many paths of the shifter are non-robustly testable and we give a path selection method so as all the selected paths to be robustly testable by 20*log/sub 2/n+2 test-vector pairs, where n is the length of the shifter. The propagation delay along all other paths is a function of the delays along the selected paths.","PeriodicalId":127222,"journal":{"name":"Proceedings Ninth Great Lakes Symposium on VLSI","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131566173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Assessing defect coverage of memory testing algorithms 评估内存测试算法的缺陷覆盖率
Proceedings Ninth Great Lakes Symposium on VLSI Pub Date : 1999-03-04 DOI: 10.1109/GLSV.1999.757450
V. Kim, Tom Chen
{"title":"Assessing defect coverage of memory testing algorithms","authors":"V. Kim, Tom Chen","doi":"10.1109/GLSV.1999.757450","DOIUrl":"https://doi.org/10.1109/GLSV.1999.757450","url":null,"abstract":"This paper describes the defect coverage evaluation of memory testing algorithms. Realistic CMOS defects were extracted from a 2/spl times/2 SRAM layout using an IFA tool, and circuit simulations were performed to measure the defect coverages of the eleven memory testing algorithms.","PeriodicalId":127222,"journal":{"name":"Proceedings Ninth Great Lakes Symposium on VLSI","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115350926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A multiple-input single-phase clock flip-flop family 多输入单相时钟触发器系列
Proceedings Ninth Great Lakes Symposium on VLSI Pub Date : 1999-03-04 DOI: 10.1109/GLSV.1999.757423
R. Hobson, Allan R. Dyck
{"title":"A multiple-input single-phase clock flip-flop family","authors":"R. Hobson, Allan R. Dyck","doi":"10.1109/GLSV.1999.757423","DOIUrl":"https://doi.org/10.1109/GLSV.1999.757423","url":null,"abstract":"The design of a versatile CMOS semi-static true singlephase clock flip-flop family is presented. It naturally supports multiple, multiplexed, inputs. Asynchronous Set/Reset are easily implemented. Switching power is lower than for some other semi-static flip-flop techniques.","PeriodicalId":127222,"journal":{"name":"Proceedings Ninth Great Lakes Symposium on VLSI","volume":"885 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116168092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel low power low phase-noise PLL architecture for wireless transceivers 一种新型的无线收发器低功耗低相位噪声锁相环结构
Proceedings Ninth Great Lakes Symposium on VLSI Pub Date : 1999-03-04 DOI: 10.1109/GLSV.1999.757439
A. Hafez, M. Elmasry
{"title":"A novel low power low phase-noise PLL architecture for wireless transceivers","authors":"A. Hafez, M. Elmasry","doi":"10.1109/GLSV.1999.757439","DOIUrl":"https://doi.org/10.1109/GLSV.1999.757439","url":null,"abstract":"A sample-and-hold stage placed in the feedback path of a PLL frequency synthesizer reduces the division ratio, and hence the phase-detector phase-noise, without the need of multiple loops, when used in conjunction with a DDS, this architecture simplifies the DDS design leading to a low-power architecture. Furthermore, this architecture allows for a large loop bandwidth thus suppressing the VCO phase-noise. The advantages of this architecture are highlighted and system- and circuit-level simulations presented.","PeriodicalId":127222,"journal":{"name":"Proceedings Ninth Great Lakes Symposium on VLSI","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123712644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Fault coverage estimation for early stage of VLSI design 超大规模集成电路设计初期的故障覆盖估计
Proceedings Ninth Great Lakes Symposium on VLSI Pub Date : 1999-03-04 DOI: 10.1109/GLSV.1999.757387
V. Kim, Tom Chen, Mick Tegethoff
{"title":"Fault coverage estimation for early stage of VLSI design","authors":"V. Kim, Tom Chen, Mick Tegethoff","doi":"10.1109/GLSV.1999.757387","DOIUrl":"https://doi.org/10.1109/GLSV.1999.757387","url":null,"abstract":"This paper proposes a new fault coverage estimation model which can be used in the early stage of VLSI design. The fault coverage model is an exponentially decaying function with three parameters, which include the fault coverage upper bound, UB, the fault coverage lower bound, LB, and the rate of fault coverage change, /spl alpha/. The fault coverages using three different testing scenarios, which are no DFT, scan, iddq testing, are predicted using circuit design information, such as gate count, I/O count, and FF count. These parameters are often readily available at the early stage of VLSI design. Finally, the composite fault coverage is estimated by combining different fault coverages. Experimental result showed a 1.9% model estimation error with a given circuit information in the early design.","PeriodicalId":127222,"journal":{"name":"Proceedings Ninth Great Lakes Symposium on VLSI","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126137490","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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