A novel low power low phase-noise PLL architecture for wireless transceivers

Abstract

A sample-and-hold stage placed in the feedback path of a PLL frequency synthesizer reduces the division ratio, and hence the phase-detector phase-noise, without the need of multiple loops, when used in conjunction with a DDS, this architecture simplifies the DDS design leading to a low-power architecture. Furthermore, this architecture allows for a large loop bandwidth thus suppressing the VCO phase-noise. The advantages of this architecture are highlighted and system- and circuit-level simulations presented.