{"title":"Numerical tools for fracture of MEMS devices","authors":"N. Tayebi, A. Tayebi, Y. Belkacemi","doi":"10.1109/GLSV.1999.757432","DOIUrl":"https://doi.org/10.1109/GLSV.1999.757432","url":null,"abstract":"Numerical tools to model fracture in MEMS devices are proposed. The two procedures are the Element Free method and the Displacement Discontinuity Method. Experiments on MEMS fracture are used to evaluate the numerical procedures. The test specimens covered a range of geometries and designs, including notches, holes and corners. For some specimens both methods gave acceptable results compared to experiments (Ballarini et al. and Suwito), while for others results were off by more than 15%. These findings raise new questions about the applicability of linear elastic fracture mechanics to model failure of MEMS devices at the microscopic scale.","PeriodicalId":127222,"journal":{"name":"Proceedings Ninth Great Lakes Symposium on VLSI","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114784769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reducing BDD size by exploiting structural connectivity","authors":"R. L. Wright, M. Shanblatt","doi":"10.1109/GLSV.1999.757394","DOIUrl":"https://doi.org/10.1109/GLSV.1999.757394","url":null,"abstract":"Computer-aided design tools have been limited by the use of the Binary Decision Diagram (BDD). The major drawback of the BDD is its abundant usage of CPU time and memory. Techniques such as BDD variable ordering and sharing have been used in the past to address the size issue. However these techniques remain to be limited to modest-sized circuits. In this paper, we present a significant variation to the conventional BDD, the Connective Binary Decision Diagram (CBDD). The CBDD addresses the size issue concerning conventional BDD implementations by employing the use of minimized-scalable binary decision diagrams (MSBDDs) combined with the structural connectivity present in the circuit's netlist. The experimental results section will demonstrate that the proposed method reduces the BDD size by more than two orders of magnitude for large circuits.","PeriodicalId":127222,"journal":{"name":"Proceedings Ninth Great Lakes Symposium on VLSI","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116271798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Routability prediction for hierarchical FPGAs","authors":"Wei Li, D. Banerji","doi":"10.1109/GLSV.1999.757428","DOIUrl":"https://doi.org/10.1109/GLSV.1999.757428","url":null,"abstract":"This paper investigates the problem of routability prediction in a FPGA that employs a hierarchical routing architecture. Such a FPGA is called a hierarchical FPGA (HFPGA). A novel model is proposed to analyze various HFPGA configurations. A software tool has been developed to predict the routability of circuits on specific HFPGA architectures. Primary contribution of this work is that routability prediction can be done immediately after the technology-mapping step, rather than after placement. The effect of connection block and switch block flexibility on routability is also studied. The results show that compared to a symmetrical FPGA architecture we can achieve the same degree of routability on a HFPGA, with much fewer routing switches.","PeriodicalId":127222,"journal":{"name":"Proceedings Ninth Great Lakes Symposium on VLSI","volume":"26 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120993278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"New 2 Gbit/s CMOS I/O pads","authors":"G. Masera, G. Piccinini, M. R. Roch, M. Zamboni","doi":"10.1109/GLSV.1999.757382","DOIUrl":"https://doi.org/10.1109/GLSV.1999.757382","url":null,"abstract":"A couple of low complexity high performance input and output pads are proposed: they have been designed in 0.7 /spl mu/m CMOS ES2 technology and support bit rates ranging from DC up to 2 Gbit/s. The differential input pad and the differential output pad interface true PECL external logic levels to full swing 5 V CMOS internal levels.","PeriodicalId":127222,"journal":{"name":"Proceedings Ninth Great Lakes Symposium on VLSI","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123909689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Memory chip BIST architecture","authors":"J. Savir","doi":"10.1109/GLSV.1999.757462","DOIUrl":"https://doi.org/10.1109/GLSV.1999.757462","url":null,"abstract":"This paper describes a random access memory (RAM, sometimes also called an array) test scheme that has the following attributes: 1. Can be used in both built-in mode and off chip/module mode. 2. Can be used to test and diagnose naked arrays. 3. Fault diagnosis is simple and is \"free\" for some faults during test. 4. Is never subject to aliasing. 5. Depending upon the test length, it can detect many kinds of failures, like stuck-cells, decoder faults, shorts, pattern-sensitive, etc. 6. If used as a built-in feature, it does not slow down the normal operation of the array. 7. Does not require storage of correct responses. A single response bit always indicates whether a fault has been detected. Thus, the storage requirement for the implementation of the test scheme is zero. 8. If used as a built-in feature, the hardware overhead is very low.","PeriodicalId":127222,"journal":{"name":"Proceedings Ninth Great Lakes Symposium on VLSI","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124852342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Clustered table-based macromodels for RTL power estimation","authors":"Roberto Corgnati, E. Macii, M. Poncino","doi":"10.1109/GLSV.1999.757455","DOIUrl":"https://doi.org/10.1109/GLSV.1999.757455","url":null,"abstract":"Macromodeling is considered the most effective approach to RTL power estimation. Among the macromodels presented in the literature, table-based ones have overcome some of the limitations of conventional, equation-based solutions. In this paper we propose some enhancements to the basic implementation of table-based macromodels that improve the estimation accuracy while preserving the intrinsic robustness.","PeriodicalId":127222,"journal":{"name":"Proceedings Ninth Great Lakes Symposium on VLSI","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123066722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Secareanu, I. Kourtev, J. Becerra, T. E. Watrobski, C. Morton, W. Staub, T. Tellier, E. Friedman
{"title":"Noise immunity of digital circuits in mixed-signal smart power systems","authors":"R. Secareanu, I. Kourtev, J. Becerra, T. E. Watrobski, C. Morton, W. Staub, T. Tellier, E. Friedman","doi":"10.1109/GLSV.1999.757441","DOIUrl":"https://doi.org/10.1109/GLSV.1999.757441","url":null,"abstract":"Experimental data describing circuit and physical design issues that influence the noise immunity of digital latches in mixed-signal smart power circuits are described and discussed. The principal result of this paper is the characterization of the conditions under which substrate noise generated by high power analog circuitry affects digital latches. The experimental data characterize a variety of different noise mitigation techniques for the particular process technology circuit structures, signal/clocking interdependencies, and related conditions.","PeriodicalId":127222,"journal":{"name":"Proceedings Ninth Great Lakes Symposium on VLSI","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114072059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Goodnick, J. Bird, D. Ferry, A. Gunther, M. Khoury, M. Kozicki, M. J. Rack, T. Thornton, D. Vasileska-Kafedezka
{"title":"Transport in split gate MOS quantum dot structures","authors":"S. Goodnick, J. Bird, D. Ferry, A. Gunther, M. Khoury, M. Kozicki, M. J. Rack, T. Thornton, D. Vasileska-Kafedezka","doi":"10.1109/GLSV.1999.757466","DOIUrl":"https://doi.org/10.1109/GLSV.1999.757466","url":null,"abstract":"A novel technique has been developed for the fabrication of Si quantum dot structures with controllable electron number through both top and side gates. We have tested devices ranging in size from 40 to 200 nm. By varying the density with the top gate, and controlling the input and output barriers of the dot with the side gates, conductance peaks are observed which map details of the energy level within the dot as well as the interaction of the electrons with one another.","PeriodicalId":127222,"journal":{"name":"Proceedings Ninth Great Lakes Symposium on VLSI","volume":"147 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127513645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An exact analytical time-domain model of distributed RC interconnects for high speed nonlinear circuit applications","authors":"N. Lu, I. Hajj","doi":"10.1109/GLSV.1999.757379","DOIUrl":"https://doi.org/10.1109/GLSV.1999.757379","url":null,"abstract":"Accurate simulation of interconnect effects is an increasingly critical step in high speed deep submicron design. With ever increasing frequency of digital/analog signals, the traditional lumped RC elements may not be accurate enough in modeling RC interconnects in VLSI applications due to the distributed nature of realistic interconnects. In this paper a novel analytic time-domain model for distributed RC interconnects is developed for application in nonlinear circuit simulators. The exact analytical solution is derived under the assumption of piecewise-linear signal waveforms at the two ports of the line. We have incorporated this model into a general purpose circuit simulator using the SWEC technique.","PeriodicalId":127222,"journal":{"name":"Proceedings Ninth Great Lakes Symposium on VLSI","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123388310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Self-checking of FPGA-based control units","authors":"I. Levin, V. Sinelnikov","doi":"10.1109/GLSV.1999.757436","DOIUrl":"https://doi.org/10.1109/GLSV.1999.757436","url":null,"abstract":"The paper introduces a new technique for on-line checking of FPGA based Control Units (CUs). This technique is based on the architecture comprising two portions. A self-checking CU and a separate totally self-checking (TSC) checker. Each of these portions is implemented as a combination of an Evolution block and an Execution block. Comparison of code vectors being transferred between the blocks of the portions enables providing a totally self-checking property. The self-checking CU is implemented in a form of a one-rail network of interconnected pre-designed LUT-based configurable logical blocks. The self-checking checker is a Sum-Of-Minterms based checker. The proposed technique: a) does not require any encoding of output words; and b) uses one-rail design, thereby drastically decreasing the required overhead.","PeriodicalId":127222,"journal":{"name":"Proceedings Ninth Great Lakes Symposium on VLSI","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116932389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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