评估内存测试算法的缺陷覆盖率

Proceedings Ninth Great Lakes Symposium on VLSI Pub Date : 1999-03-04 DOI:10.1109/GLSV.1999.757450

V. Kim, Tom Chen

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引用次数: 3

摘要

本文描述了内存测试算法的缺陷覆盖率评估。利用IFA工具从2/spl times/2 SRAM布局中提取出真实的CMOS缺陷，并进行电路仿真，测量了11种存储器测试算法的缺陷覆盖率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Assessing defect coverage of memory testing algorithms

This paper describes the defect coverage evaluation of memory testing algorithms. Realistic CMOS defects were extracted from a 2/spl times/2 SRAM layout using an IFA tool, and circuit simulations were performed to measure the defect coverages of the eleven memory testing algorithms.

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Proceedings Ninth Great Lakes Symposium on VLSI

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