Congestion mitigation during placement

Abstract

High post-placement congestion in complex ASICs and microprocessors may pose severe constraints on the wiring resources, thereby causing wireability, timing and noise problems. Linear wirelength-based mincut partitioning algorithms have some built-in advantages for reducing congestion. We present a mathematical model of congestion and experimentally investigate various congestion mitigation techniques used in conjunction with linear wirelength-based placement. The experimental results validate our congestion model. Our placement tool, CPlace(C), is a clustering-based mincut partitioner that optimizes a linear wirelength objective.