Fault coverage estimation for early stage of VLSI design

Abstract

This paper proposes a new fault coverage estimation model which can be used in the early stage of VLSI design. The fault coverage model is an exponentially decaying function with three parameters, which include the fault coverage upper bound, UB, the fault coverage lower bound, LB, and the rate of fault coverage change, /spl alpha/. The fault coverages using three different testing scenarios, which are no DFT, scan, iddq testing, are predicted using circuit design information, such as gate count, I/O count, and FF count. These parameters are often readily available at the early stage of VLSI design. Finally, the composite fault coverage is estimated by combining different fault coverages. Experimental result showed a 1.9% model estimation error with a given circuit information in the early design.