发布求助
文献互助 智能选刊 最新文献

2018 International SoC Design Conference (ISOCC)最新文献

筛选
英文 中文
Estimation of Leakage Distribution Utilizing Gaussian Mixture Model 利用高斯混合模型估计泄漏分布
2018 International SoC Design Conference (ISOCC) Pub Date : 2018-11-01 DOI: 10.1109/ISOCC.2018.8649978
Hyun-jeong Kwon, Young Hwan Kim, Seokhyeong Kang
{"title":"Estimation of Leakage Distribution Utilizing Gaussian Mixture Model","authors":"Hyun-jeong Kwon, Young Hwan Kim, Seokhyeong Kang","doi":"10.1109/ISOCC.2018.8649978","DOIUrl":"https://doi.org/10.1109/ISOCC.2018.8649978","url":null,"abstract":"In this paper, we propose a novel method which utilizes the Gaussian Mixture Model (GMM) to estimate the leakage distribution of a circuit. Our proposed method assumes that the leakage distribution can be represented using the GMM which can cover any continuous function. After the GMM clustering using the leakage simulation data, the leakage distribution of the input circuit can be obtained. The experimental results with the K-S test showed that the proposed method exhibited 1.82e+05 times larger p-value and 7.74e-01 times smaller K-S statistics compared to the state-of-the-art benchmark method on average.","PeriodicalId":127156,"journal":{"name":"2018 International SoC Design Conference (ISOCC)","volume":"13 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125823214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fixed-Point Quantization of 3D Convolutional Neural Networks for Energy-Efficient Action Recognition 节能动作识别中三维卷积神经网络的定点量化
2018 International SoC Design Conference (ISOCC) Pub Date : 2018-11-01 DOI: 10.1109/ISOCC.2018.8649987
Hyunhoon Lee, Younghoon Byun, Seokha Hwang, Sunggu Lee, Youngjoo Lee
{"title":"Fixed-Point Quantization of 3D Convolutional Neural Networks for Energy-Efficient Action Recognition","authors":"Hyunhoon Lee, Younghoon Byun, Seokha Hwang, Sunggu Lee, Youngjoo Lee","doi":"10.1109/ISOCC.2018.8649987","DOIUrl":"https://doi.org/10.1109/ISOCC.2018.8649987","url":null,"abstract":"In this paper, 3D convolutional neural networks (CNNs) are simplified to reduce the energy consumption of the action recognition process. Instead of using floating-point weights and input values, which results in a huge amount of processing energy, we introduce a systematic way to quantize all the values of 3D CNNs without degrading the recognition accuracy. Simulation results show that, compared to the baseline CNN architecture, the proposed method significantly reduces the computational complexity as well as the memory requirements.","PeriodicalId":127156,"journal":{"name":"2018 International SoC Design Conference (ISOCC)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126721200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
12-bit 20M-S/s SAR ADC using C-R DAC and Capacitor Calibration 使用C-R DAC和电容校准的12位20M-S/s SAR ADC
2018 International SoC Design Conference (ISOCC) Pub Date : 2018-11-01 DOI: 10.1109/ISOCC.2018.8649894
Eunji Youn, Young-Chan Jang
{"title":"12-bit 20M-S/s SAR ADC using C-R DAC and Capacitor Calibration","authors":"Eunji Youn, Young-Chan Jang","doi":"10.1109/ISOCC.2018.8649894","DOIUrl":"https://doi.org/10.1109/ISOCC.2018.8649894","url":null,"abstract":"A successive approximation register (SAR) analog-to-digital converter (ADC) using a capacitor-resistor(C-R) digital-to-analog-converter (DAC) is proposed to implement the resolution of 12 bits maintaining the area for 10 bits. A calibration for upper-bit capacitors of the C-R DAC is proposed to increase the performance of the static and dynamic performances. To evaluate the proposed ADC, a 12-bit 20M-S/s SAR ADC is implemented using a 110-nm CMOS process with a supply of 1.2 V. The area and power consumption of the proposed ADC are 0.204 mm2 and 1.24 mW, respectively.","PeriodicalId":127156,"journal":{"name":"2018 International SoC Design Conference (ISOCC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122087460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Convolutional Neural Network Accelerator with Reconfigurable Dataflow 具有可重构数据流的卷积神经网络加速器
2018 International SoC Design Conference (ISOCC) Pub Date : 2018-11-01 DOI: 10.1109/ISOCC.2018.8649988
Myungwoo Oh, Chaeeun Lee, Sanghun Lee, Youngho Seo, Sunwoo Kim, Jooho Wang, C. Park
{"title":"Convolutional Neural Network Accelerator with Reconfigurable Dataflow","authors":"Myungwoo Oh, Chaeeun Lee, Sanghun Lee, Youngho Seo, Sunwoo Kim, Jooho Wang, C. Park","doi":"10.1109/ISOCC.2018.8649988","DOIUrl":"https://doi.org/10.1109/ISOCC.2018.8649988","url":null,"abstract":"Convolutional-Neural-Network (CNN) is used in broad applications. There are dataflows for convolutional layers in CNN such as row-stationary and weight-stationary. However, these dataflows have strengths and weaknesses. This paper analyzed two representative dataflows and introduce the dataflow-reconfigurable CNN accelerator that takes advantage of both dataflows.","PeriodicalId":127156,"journal":{"name":"2018 International SoC Design Conference (ISOCC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114853712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design of 3D Inductors for IoT Security 物联网安全3D电感器的设计
2018 International SoC Design Conference (ISOCC) Pub Date : 2018-11-01 DOI: 10.1109/ISOCC.2018.8649908
Bruce C. Kim, Sang-Bock Cho
{"title":"Design of 3D Inductors for IoT Security","authors":"Bruce C. Kim, Sang-Bock Cho","doi":"10.1109/ISOCC.2018.8649908","DOIUrl":"https://doi.org/10.1109/ISOCC.2018.8649908","url":null,"abstract":"This paper describes the design of through-silicon via (TSV)-based inductors for security of Internet-of-Things (IoT). We designed 3D inductors with security hardware using physically unclonable function (PUF) circuit. The secure 3D inductor could be tuned to desirable frequency by using MEMS switches.","PeriodicalId":127156,"journal":{"name":"2018 International SoC Design Conference (ISOCC)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130154476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Energy Efficient Analog Synapse/Neuron Circuit for Binarized Neural Networks 二值化神经网络的高能效模拟突触/神经元电路
2018 International SoC Design Conference (ISOCC) Pub Date : 2018-11-01 DOI: 10.1109/ISOCC.2018.8649929
Jaehyun Kim, Chaeun Lee, Kiyoung Choi
{"title":"Energy Efficient Analog Synapse/Neuron Circuit for Binarized Neural Networks","authors":"Jaehyun Kim, Chaeun Lee, Kiyoung Choi","doi":"10.1109/ISOCC.2018.8649929","DOIUrl":"https://doi.org/10.1109/ISOCC.2018.8649929","url":null,"abstract":"Energy efficiency is one of the most important factors to make deep neural networks viable in embedded systems. In this paper, we propose an analog synapse circuit using resistive random access memory (ReRAM) which operates with a switched capacitor neuron for binarized neural networks (BNNs). Thanks to the compact and energy efficient ReRAM synapses, the circuit simulation results of an MLP implemented with the proposed synapse and neuron circuits show 2.5ns classification latency and very high energy efficiency of 1536TOPS/W on 32nm technology.","PeriodicalId":127156,"journal":{"name":"2018 International SoC Design Conference (ISOCC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131647342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Reconfigurable Multi-Input Adder Design for Deep Neural Network Accelerators 深度神经网络加速器的可重构多输入加法器设计
2018 International SoC Design Conference (ISOCC) Pub Date : 2018-11-01 DOI: 10.1109/ISOCC.2018.8649943
Hossein Moradian, Sujeong Jo, Kiyoung Choi
{"title":"Reconfigurable Multi-Input Adder Design for Deep Neural Network Accelerators","authors":"Hossein Moradian, Sujeong Jo, Kiyoung Choi","doi":"10.1109/ISOCC.2018.8649943","DOIUrl":"https://doi.org/10.1109/ISOCC.2018.8649943","url":null,"abstract":"This paper proposes two efficient designs of reconfigurable multi-input adders for deep neural network accelerators. The reconfigurability allows us to use resources in different ways optimized to different applications. The designed adders enable bit-width adaptive computing in neural network layers, which improves computing throughput. The proposed designs are implemented with 45nm CMOS TSMC library and the results show that the proposed modules achieve throughput much higher than that of conventional designs even with the reconfigurability without significant hardware overhead.","PeriodicalId":127156,"journal":{"name":"2018 International SoC Design Conference (ISOCC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131000804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi-Mode LSTM Network for Energy-Efficient Speech Recognition 节能语音识别的多模LSTM网络
2018 International SoC Design Conference (ISOCC) Pub Date : 2018-11-01 DOI: 10.1109/ISOCC.2018.8649913
Junseo Jo, Seokha Hwang, Sunggu Lee, Youngjoo Lee
{"title":"Multi-Mode LSTM Network for Energy-Efficient Speech Recognition","authors":"Junseo Jo, Seokha Hwang, Sunggu Lee, Youngjoo Lee","doi":"10.1109/ISOCC.2018.8649913","DOIUrl":"https://doi.org/10.1109/ISOCC.2018.8649913","url":null,"abstract":"We newly introduce a novel processing scenario of long short-term memory (LSTM) network for the energy-efficient speech recognition. Compared to the conventional single-mode processing based on the fixed computing scheme, the proposed LSTM processing contains multiple operating cells providing attractive tradeoff between the recognition accuracy and the energy consumption. For the case study, the state-of-the-art LSTM network is modified to have two types of processing cells, strong and weak cells, which are dedicated to the accuracy-aware and energy-aware LSTM sequences, respectively. By allocating as many weak cells with low energy as possible, experimental results show that the proposed work saves the energy consumption for speech recognition by 75% compared to the original network.","PeriodicalId":127156,"journal":{"name":"2018 International SoC Design Conference (ISOCC)","volume":"201 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115701286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
The Hardware Acceleration of SC Decoder for Polar Code towards HLS Optimization 面向HLS优化的极性码SC解码器硬件加速
2018 International SoC Design Conference (ISOCC) Pub Date : 2018-11-01 DOI: 10.1109/ISOCC.2018.8649940
Yujie Huang, Yujie Cai, Ming-e Jing, Jun Han, Yibo Fan, Xiaoyang Zeng
{"title":"The Hardware Acceleration of SC Decoder for Polar Code towards HLS Optimization","authors":"Yujie Huang, Yujie Cai, Ming-e Jing, Jun Han, Yibo Fan, Xiaoyang Zeng","doi":"10.1109/ISOCC.2018.8649940","DOIUrl":"https://doi.org/10.1109/ISOCC.2018.8649940","url":null,"abstract":"With the extensive use of hardware acceleration for complex algorithms, fast hardware implementations of those algorithms with HLS become necessary. However, high performance hardware generated with HLS needs numerous skills and the successive-cancellation (SC) decoding algorithm for polar code, which is widely used in 5G era, can’t be converted from c code to verilog code with HLS directly because of the recursion in it. In this paper, we firstly find out the operation laws of SC decoding algorithm; secondly, we expand the recursion in the SC decoding algorithm according to the laws; thirdly, we convert float point data to fixed point which reduces LUT resources by 63.5% and simplify the function consisting of exponential and logarithm operation through Taylor Expansion to reduce hardware resource and accelerate the hardware; finally, we apply pipeline in for loop which reduces cycles by 29% and call on-chip RAM in HLS to quickly generate high performance SC decoder which consumes low hardware resources.","PeriodicalId":127156,"journal":{"name":"2018 International SoC Design Conference (ISOCC)","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114435416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 28-GHz 28.5-dBm power amplifier using 0.15-µm InGaAs E-mode pHEMT technology 采用0.15µm InGaAs E-mode pHEMT技术的28ghz 28.5 dbm功率放大器
2018 International SoC Design Conference (ISOCC) Pub Date : 2018-11-01 DOI: 10.1109/ISOCC.2018.8649905
Hui-Dong Lee, Sunwoo Kong, Bonghyuk Park, Kwangchun Lee, Jeongsoo Park, Jeong‐Geun Kim
{"title":"A 28-GHz 28.5-dBm power amplifier using 0.15-µm InGaAs E-mode pHEMT technology","authors":"Hui-Dong Lee, Sunwoo Kong, Bonghyuk Park, Kwangchun Lee, Jeongsoo Park, Jeong‐Geun Kim","doi":"10.1109/ISOCC.2018.8649905","DOIUrl":"https://doi.org/10.1109/ISOCC.2018.8649905","url":null,"abstract":"This paper describes the design of a 28-GHz 28.5-dBm power amplifier using a 0.15-µm InGaAs E-mode pHEMT technology. We have sought a method to obtain the required output power through the characteristics of the unit transistor provided by the manufacturer. For this purpose, the PA circuit is configured to effectively combine the output signals of eight unit transistors. As a result of the verification, 28.5-dBm output was obtained at 28-GHz and the maximum efficiency was more than 24.5%. The power amplifier draws 335 mA under a 6.4 V supply at 28.5-dBm output.","PeriodicalId":127156,"journal":{"name":"2018 International SoC Design Conference (ISOCC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114822974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信