12-bit 20M-S/s SAR ADC using C-R DAC and Capacitor Calibration

Abstract

A successive approximation register (SAR) analog-to-digital converter (ADC) using a capacitor-resistor(C-R) digital-to-analog-converter (DAC) is proposed to implement the resolution of 12 bits maintaining the area for 10 bits. A calibration for upper-bit capacitors of the C-R DAC is proposed to increase the performance of the static and dynamic performances. To evaluate the proposed ADC, a 12-bit 20M-S/s SAR ADC is implemented using a 110-nm CMOS process with a supply of 1.2 V. The area and power consumption of the proposed ADC are 0.204 mm2 and 1.24 mW, respectively.