The Hardware Acceleration of SC Decoder for Polar Code towards HLS Optimization

Abstract

With the extensive use of hardware acceleration for complex algorithms, fast hardware implementations of those algorithms with HLS become necessary. However, high performance hardware generated with HLS needs numerous skills and the successive-cancellation (SC) decoding algorithm for polar code, which is widely used in 5G era, can’t be converted from c code to verilog code with HLS directly because of the recursion in it. In this paper, we firstly find out the operation laws of SC decoding algorithm; secondly, we expand the recursion in the SC decoding algorithm according to the laws; thirdly, we convert float point data to fixed point which reduces LUT resources by 63.5% and simplify the function consisting of exponential and logarithm operation through Taylor Expansion to reduce hardware resource and accelerate the hardware; finally, we apply pipeline in for loop which reduces cycles by 29% and call on-chip RAM in HLS to quickly generate high performance SC decoder which consumes low hardware resources.