Reconfigurable Multi-Input Adder Design for Deep Neural Network Accelerators

Abstract

This paper proposes two efficient designs of reconfigurable multi-input adders for deep neural network accelerators. The reconfigurability allows us to use resources in different ways optimized to different applications. The designed adders enable bit-width adaptive computing in neural network layers, which improves computing throughput. The proposed designs are implemented with 45nm CMOS TSMC library and the results show that the proposed modules achieve throughput much higher than that of conventional designs even with the reconfigurability without significant hardware overhead.