2015 28th International Conference on VLSI Design最新文献

{"title":"Ultra-fast Cap-less LDO for Dual Lane USB in 28FDSOI","authors":"S. Singh, Gautam Dey Kanungo","doi":"10.1109/VLSID.2015.49","DOIUrl":"https://doi.org/10.1109/VLSID.2015.49","url":null,"abstract":"A fully on-chip LDO for very fast load transient up to 15mA/nsec in 28nm FDSOI is presented. Proposed LDO capitalizes on technological boost given to on-chip capacitance density and MOS current drives to implement conventional compensation technique without using off-chip capacitor. Dominant output pole enables the LDO to achieve its superior load transient performance. Proposed LDO generates 1.0V output from a 1.6V input supply and has maximum output current capacity of 15mA. Simulated worst case PSR at 10kHz is-23dB and current efficiency is 93% at maximum load condition. Three such LDOs are combined to provide dedicated 1.0V supplies to dual lane USB cores and their PLL. Area including reference generator, three LDO and all on-chip capacitances is 0.2mm2.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"598 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125235225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tutorial T2: Validation and Debug of Security and Trust Issues in Embedded Systems","authors":"P. Mishra, S. Bhunia, S. Ravi","doi":"10.1109/VLSID.2015.110","DOIUrl":"https://doi.org/10.1109/VLSID.2015.110","url":null,"abstract":"Summary form only given. Reusable hardware intellectual property (IP) based System-on-Chip (SoC) design has emerged as a pervasive design practice in the industry to dramatically reduce design/verification cost while meeting aggressive time-to-market constraints. However, growing reliance on reusable pre-verified hardware IPs and wide array of CAD tools during SoC design - often gathered from untrusted 3rd party vendors - severely affects the security and trustworthiness of SoC computing platforms. Major security issues in the hardware IPs at different stages of SoC life cycle include piracy during IP evaluation, reverse engineering, cloning, counterfeiting, as well as malicious hardware modifications. The global electronic piracy market is growing rapidly and is now estimated to be $1B/day, of which a significant part is related to hardware IPs. Furthermore, use of untrusted foundry in a fabless business model greatly aggravates the SoC security threats by introducing vulnerability of malicious modifications or piracy during SoC fabrication. Due to ever-growing computing demands, modern SoCs tend to include many heterogeneous processing cores, scalable communication network, together with reconfigurable cores e.g. embedded FPGA in order to incorporate logic that is likely to change as standards and requirements evolve. Such design practices greatly increase the number of untrusted components in the SoC design flow and make the overall system security a pressing concern. There is a critical need to analyze the SoC security issues and attack models due to involvement of multiple untrusted entities in SoC design cycle - IP vendors, CAD tool developers, and foundries - and develop low-cost effective countermeasures. These countermeasures would encompass encryption, obfuscation, watermarking and fingerprinting, and certain analytic methods derived from the behavioral aspects of SoC to enable trusted operation with untrusted components. In this tutorial, we plan to provide a comprehensive coverage of both fundamental concepts and recent advances in validation of security and trust of hardware IPs. The tutorial also covers the security and debug trade-offs in modern SoCs e.g., more observability is beneficial for debug whereas limited observability is better for security. It examines the state-of-the-art in research in this challenging area as well as industrial practice, and points to important gaps that need to be filled in order to develop a validation and debug flow for secure SoC systems. The tutorial presenters (one industry expert and two faculty members) will be able to provide unique perspectives on both academic research and industrial practices. The selection of topics covers a broad spectrum and will be of interest to a wide audience including design, validation, security, and debug engineers. The proposed tutorial consists of five parts. The first part introduces security vulnerabilities and various challenges associated with trust validat","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"19 1 Pt 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116481753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Recursive Model for Smooth Approximation to Wirelength and Its Impact on Analytical Placement","authors":"B. Ray, S. Balachandran","doi":"10.1109/VLSID.2015.76","DOIUrl":"https://doi.org/10.1109/VLSID.2015.76","url":null,"abstract":"Analytical placement engines use half-perimeter wire length (HPWL) of the circuit as an objective function to place blocks optimally within a chip. Inspired by popularly used log sum-exp (LSE) wire length model [6], ABS wire length model [5] and weighted average (WA) wire length model [3], we propose a new recursive wire length model for HPWL, providing smooth approximation to the max function. We show that the accuracy of the new model is better than that of LSE, WA and ABS wire length models, both theoretically and experimentally. When deployed inside an analytical engine, we show that our model provides more than 12% reduction in wire length compared to LSE at the expense of 50% more runtime. We also observed that the proposed model and the existing iterative models differ in their impact on the relative effort that has to be put in at the global placement vs. The detailed placement phase.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130819027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On the Analysis of Reversible Booth's Multiplier","authors":"J. Sultana, Sajib Kumar Mitra, A. Chowdhury","doi":"10.1109/VLSID.2015.34","DOIUrl":"https://doi.org/10.1109/VLSID.2015.34","url":null,"abstract":"Reversible logic attains the attraction of researchers in the last decade mainly due to low-power dissipation. Designers' endeavors are thus continuing in creating complete reversible circuits consisting of reversible gates. This paper presents a design methodology for the realization of Booth's multiplier in reversible mode. Booth's multiplier is considered as one of the fastest multipliers in literature and we have shown an efficient design methodology in reversible paradigm. The proposed architecture is capable of performing both signed and unsigned multiplication of two operands without having any feedbacks, whereas existing multipliers in reversible mode consider loop which is strictly prohibited in reversible logic design. Theoretical underpinnings, established for the proposed design, show that the proposed circuit is very efficient from reversible circuit design point of view.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129379651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation","authors":"V. Devanathan, Lakshmanan Balasubramanian, R. Parekhji","doi":"10.1109/VLSID.2015.67","DOIUrl":"https://doi.org/10.1109/VLSID.2015.67","url":null,"abstract":"With SOCs being increasingly designed for communication and embedded processing applications, the content of analog, mixed-signal (AMS) and RF components in them has increased. Large SOCs are often dominated by these components, which in turn also contribute to the overall incurred test time, attainable test quality and time required for silicon debug and characterisation. Existing test methods based on the use of specification based tests and use of design verification test-benches are increasingly difficult to adopt in such SOCs (as compared to standalone IP chips) since a large number of such modules and their interactions must be tested in the budgeted test time. The paper describes the practical use of fault simulation for AMS circuits to address the above issues. The main contributions of this paper are two-fold. (i) Enhancements are proposed to a commercially available analog fault simulation flow to handle specific SOC requirements of accuracy and speed, using smart management of models and/or fault lists across different fault conditions and fault sites. (ii) Efficient test generation methods targeting the analog -- digital interface are built by identifying uncovered regions/operating modes of the circuit. These are novel extensions to the commercial analog EDA tools supporting regular fault simulation. Experiments are performed on industrial designs and benefits are highlighted. It is expected that such techniques will be increasingly required to be integrated into the design flows for mixed-signal SOCs.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128880606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"DFT Technique for Quick Characterization of Flash Offset in Pipeline ADCs","authors":"P. Nair, N. Viswanathan","doi":"10.1109/VLSID.2015.69","DOIUrl":"https://doi.org/10.1109/VLSID.2015.69","url":null,"abstract":"This paper proposes a novel DFT block and associated method for characterizing the offsets of the coarse flash used in a pipelined ADC. In non-SHA architecture, due to the presence of dynamic offset, measuring flash offsets across input frequency becomes important. By adding special data output modes, the proposed DFT technique allows speedy characterization of flash offset, across PVT, using the standard single-tone test and measurement setup for the ADCs.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117196078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Robot Navigation Using Neuro-electronic Hybrid Systems","authors":"J. B. George, G. Abraham, B. Amrutur, S. Sikdar","doi":"10.1109/VLSID.2015.21","DOIUrl":"https://doi.org/10.1109/VLSID.2015.21","url":null,"abstract":"Neuro-electronic hybrid systems have been gaining interest of researchers as a possible architecture for computing. This aims to exploit the strengths of biological neuronal systems with their immense parallel processing and learning capabilities along with that of VLSI systems. Towards this end, we have set up a system which demonstrates the use of a live neuronal culture to solve a real world problem of controlling a robot doing the task of obstacle avoidance. We show that a neuronal culture can look at the sensor inputs to the robot and generate motor commands to allow it to explore an arena while avoiding obstacles.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124208254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT Using 9/7 and 5/3 Filters","authors":"P. Meher, B. K. Mohanty, M. Swamy","doi":"10.1109/VLSID.2015.61","DOIUrl":"https://doi.org/10.1109/VLSID.2015.61","url":null,"abstract":"This paper presents an optimized adder-based formulation for low-area and low-power implementation of 1-D DWT using 5/3 and 9/7 filters. Not only the number of adders is minimized, the number bit-shifts also minimized in the formulation to reduce the bit-width of intermediate results. Separate Adder-based designs are derived using the proposed formulation for 9/7 filter, 5/3 filter and a reconfigurable structure for both 9/7 and 5/3 filters. The proposed structure for 9/7 filter requires 19 adders and 11 hardwired-shifters (shifters are implemented by rewiring only) and computes two DWT components in every clock cycle. It requires only 8 registers for two-stage pipeline implementation. The proposed reconfigurable structure involves a small overhead of complexity in terms of one adder, 2 MUXes, 2 registers, and 4 extra hardwired-shifters than the proposed 9/7 structure to have the reconfigurable design. The proposed reconfigurable structure supports higher usable frequency (without pipelining), and provides double the throughput per clock cycle compared to that of best available similar structure with marginally higher area complexity. ASIC synthesis results show that the proposed pipelined structure for 9/7 filters involves nearly 70% less ADP and 82% less EPO than the best of DA-based structures. Further, it involves less than half the ADP and 47% less EPO than the corresponding recent multiplier-based structure. The proposed reconfigurable structure involves less than one-third the EPO and ADP of similar existing structure. The proposed design indicates the superiority of adder-based design over DA-based design as well as conventional multiplier-based design.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114704703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis of Second-Order Effect Components of Drain Conductance and Its Implication on Output Resistance of Wilson Current Mirror","authors":"Kirmender Singh, A. Bhattacharyya","doi":"10.1109/VLSID.2015.95","DOIUrl":"https://doi.org/10.1109/VLSID.2015.95","url":null,"abstract":"Drain conductance gds is an important small signal parameter for analysis of small signal model of analog circuits as it influences the output resistance and voltage gain. The gds or reciprocal rds and Early voltage is a useful design parameter for designer as they appear frequently in intrinsic voltage gain and transresistance expression in general circuits. In this paper we analyze the different component of gds in which it can be decomposed to fifferent component as it is influenced by many second order effects like channel length modulation, vertical field mobility reduction, drain induced barrier lowering and velocity saturation. The analysis of impact of overdrive voltage and Inversion Coefficient (IC) for fixed drain voltage and shape factor on gds components is investigated. The validation of total drain conductance which is sum of its component is verified using BSIM3v3 model PTM generated data on 180nm technology node. The effect of component is shown in intrinsic voltage gain of single stage common source transistor and output resistance of Wilson current mirror as function of inversion level. The sensitivity of output resistance on process related parameters which give deeper insight of circuit performance is computed qualitatively. The interpolation equation as used by EKV model is taken for analysis and analytically computed for the different gds components.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121603202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"OcNoC: Efficient One-Cycle Router Implementation for 3D Mesh Network-on-Chip","authors":"Ramon Fernandes, Lucas Brahm, T. Webber, R. Cataldo, L. Poehls, C. Marcon","doi":"10.1109/VLSID.2015.23","DOIUrl":"https://doi.org/10.1109/VLSID.2015.23","url":null,"abstract":"The overall system-on-chip performance depends on the network architecture, whose communication latency significantly impacts on the application performance. The challenge for on-chip networks is reducing costs while providing high performance such as low latency and high throughput. One alternative to achieve such goals is to implement efficient router architectures capable of fast packet switching and routing for parallel and scalable Networks-on-Chip (NoCs). We propose a single cycle router implementation for 3D Mesh NoCs with two arbitration approaches. Our evaluations show that the proposed one-cycle router can reduce network latency up to 57% and application latency up to 67%, when compared to multistage routers. This improvement comes with minimal silicon area overhead when compared to baseline router micro architecture, while still maintaining short critical paths.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125203323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}