OcNoC: Efficient One-Cycle Router Implementation for 3D Mesh Network-on-Chip

Abstract

The overall system-on-chip performance depends on the network architecture, whose communication latency significantly impacts on the application performance. The challenge for on-chip networks is reducing costs while providing high performance such as low latency and high throughput. One alternative to achieve such goals is to implement efficient router architectures capable of fast packet switching and routing for parallel and scalable Networks-on-Chip (NoCs). We propose a single cycle router implementation for 3D Mesh NoCs with two arbitration approaches. Our evaluations show that the proposed one-cycle router can reduce network latency up to 57% and application latency up to 67%, when compared to multistage routers. This improvement comes with minimal silicon area overhead when compared to baseline router micro architecture, while still maintaining short critical paths.