2015 28th International Conference on VLSI Design最新文献

{"title":"Tutorial T9: Dealing with Startup Issues in Low Power Mixed Signal SoCs","authors":"S. Ganesan","doi":"10.1109/VLSID.2015.117","DOIUrl":"https://doi.org/10.1109/VLSID.2015.117","url":null,"abstract":"Summary form only given. While most Silicon issues found in a complex Mixed Signal System On a Chip(SoC) usually result in a long debug, design fixing and verification cycles, having an unreliable startup arguably causes the most damaging impact in productizing the SoC. This is because such issues are not always be caught in the evaluation and characterization cycles of the SoC, but could show up at a much later stage, even after it has been released for production. The condition at which the chip fails to start up as intended, usually depends on a lot of variables such as temperature, power supply ramp up/down rates, leakage paths, substrate currents or even a strong RF field in the vicinity of the SoC. Due to this, the chances of catching the exact failure mechanism either through simulations during the design phase, or during lab testing phase is quite low. Therefore, the best way to deal with startup issues is to try and eliminate the possibility of such issues completely through robust design techniques. Considering the magnitude of the problem, it is very surprising to note that there is very little published literature on startup issues and on how to design to ensure robust startup. This tutorial is intended to bridge this gap. This tutorial on “Dealing with Startup-Issues in Low Power Mixed Signal SoCs” would be a Half-day tutorial divided into three parts each of length approximately one hour. First part of the tutorial would focus on startup circuit design self-biased reference circuits such as bandgap references focusing on ultra-low power. The second part would focus on simulation techniques to catch startup issues. The third and final part would focus on startup issues faced at full chip level and conclude with a check list to ensure robust startup. The tutorial would be in three parts each of duration one hour. In the first part of the tutorial, we will look at the classic analog startup problem associated with bandgap reference circuits and other such voltage or current reference circuits. The common pitfalls and weaknesses associated with the startup of these circuits would be highlighted. We will point to a number of published papers and patents with “flawed” startup circuits. We will highlight the challenges in implementing robust startup for ultra-low power reference circuits and look at the possibility of whether a zero -power circuit that can guarantee reliable startup is possible at all. In this regard we will also discuss the usage of Native-Vt devices in startup circuits and highlight the care one needs to take while using these devices in startup circuits. In the second part of the tutorial, we will describe simulation techniques by which we can catch many startup issues. We will discuss how to identify weaknesses in a startup circuit and to quickly figure out the PVT condition in which the circuit is most likely to have a startup failure. In this regard, we will discuss how we can check the robustness of the startup circ","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122057289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Formal Methods for Pattern Based Reliability Analysis in Embedded Systems","authors":"Sumana Ghosh, P. Dasgupta","doi":"10.1109/VLSID.2015.38","DOIUrl":"https://doi.org/10.1109/VLSID.2015.38","url":null,"abstract":"A wide variety of periodic tasks in embedded systems require reliable service guarantees under a given fault distribution. Reliable execution requires the periodic task to be replicated more often under normal circumstances so that the desired service throughput is achieved under the fault distribution. This paper presents a formal approach for verifying whether an input distribution meets the desired service guarantee under a fault distribution, where all the distributions are specified in real time calculus. The proposed methodology leverages the recently discovered relationship between real time calculus specifications and omega-regular languages.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132056034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Block-Level Electro-Migration Analysis (BEMA) for Safer Product Life","authors":"Radhika Gupta, A. Bhargava, Rakeshshenoy Panemangalore","doi":"10.1109/VLSID.2015.53","DOIUrl":"https://doi.org/10.1109/VLSID.2015.53","url":null,"abstract":"With technologies like Fully Depleted Silicon On Insulator (FDSOI), the high performance transistor devices push very good Ion but the metallization is not equipped to handle it reliably for different Power-on-Hours(POH) needs. Current density is not scaling down proportionally with downscaling and hence resulting into more stress on interconnects for these advanced nodes. Traditional method of running electromigration(EM) checks at the final stage of the Intellectual Property (IP) development cycle - after integration of all building blocks at the top level - becomes a complex and time consuming activity. This method has two basic challenges - 1) Not scalable for large memory instances 2) Will take at least 2 man weeks per compiler. In this paper we present a new methodology of checking electromigration at the block level. This methodology is not restricted to Memories and can be applied to any Custom IP that is hierarchical and is developed top-down. This greatly reduces the effort needed to clean up electromigration and joule heating violations at the top level. The correlation between the full cut and block level results is within 2%. Running this analysis at block-level reduces any limit on the design size. Cumulative runtimes at block level turns out to be much smaller than a single run at the top level. This methodology saves us ~8X on the run time and ~14X on the total memory utilization. These gains are in addition to the fact that the product cycle time is reduced because we are able to run the analysis at an earlier stage where the corrections are practically possible.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134189356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Energy Aware Computation Driven Approximate DCT Architecture for Image Processing","authors":"Vikas Kaushal, Bharat Garg, Ankur Jaiswal, G. K. Sharma","doi":"10.1109/VLSID.2015.66","DOIUrl":"https://doi.org/10.1109/VLSID.2015.66","url":null,"abstract":"Energy crisis in multimedia devices causes poor image/video quality. These devices use compression standard having Discrete Cosine Transform (DCT) as core compute-intensive component. This paper presents novel approximation techniques that provide effective computation based on assumptions namely, transitive behavior of pixels, inter pixel approximation, and multiplicand value decision. We propose an energy aware computation driven approximate DCT architecture by exploiting these approximation techniques. The architecture emerges to have only 25 coefficients as an outcome which further incorporates interdependence among DCT alphabets. This inter-dependence results in squeezing of seven DCT alphabets into three. The efficacy of the proposed architecture is evaluated by different image quality assessment parameters. The architecture is mapped on Virtex - 6 FPGA to obtain top level analysis. A Semi Custom design is also realized using 45nm CMOS technology and simulated on HSIM. The simulation results show around 2.5× and 4.5× reduction in area (58%) and energy (72.6%), respectively, over existing design. This has been tested on Baseline JPEG standard for its effectiveness.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134190306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ARGUS: A Framework for Rapid Design and Prototype of Heterogeneous Multicore Systems in FPGA","authors":"Jude Angelo Ambrose, Tuo Li, Daniel Murphy, Shivam Gargg, Nick Higgins, S. Parameswaran","doi":"10.1109/VLSID.2015.10","DOIUrl":"https://doi.org/10.1109/VLSID.2015.10","url":null,"abstract":"Multicore systems are an integral part of today's embedded systems which allow for improved performance and reduced power consumption. Designing and creating a multicore system is challenging. Verification and validation of the designed multicore system incur significant cost and effort. A simpler design process will allow even the software engineers to design multicore systems and evaluate their applications for performance and power. In order to assist the designers, engineers and users alike to easily design multicore, we propose a framework in this paper which allows design and prototyping of multicore systems in an FPGA within hours. Our framework allows rapid design and automated prototyping, and improves validation and verification of the entire multicore system. Two use cases are evaluated to demonstrate the applicability of our framework.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132908341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Accelerating SVM on Ultra Low Power ASIP for High Throughput Streaming Applications","authors":"Anmol Gupta, Ashutosh Pal","doi":"10.1109/VLSID.2015.93","DOIUrl":"https://doi.org/10.1109/VLSID.2015.93","url":null,"abstract":"With increasing complexity of algorithms for embedded systems, demand for higher processor performance and lower battery power consumption is growing immensely. Due to upcoming fields like embedded vision where algorithms require learning, techniques like Support Vector Machines (SVM) have gained significant importance in these areas. These machines are required in performing classification tasks in variety of fields to analyze data, recognize patterns in images and videos. In this work, SVM is implemented on an Application Specific Instruction Processor (ASIP) designed using an Architectural Description Language (ADL) based tool to meet the ultra-high throughput and ultra-low power requirement posed by pedestrian detection algorithm in embedded vision-domain. We started with a base RISC processor and added a list of systematic extensions to gain speed for SVM like algorithms. With this we could achieve a throughput of ~630K SVMs/sec (~3k dimensions) at 6.5 mW, which is significantly better than GPU (Nvidia GTX280 at 236 Watt) in terms of power and ARM Cortex-A8 (~16K SVMs/sec) in terms of throughput.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132917781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal-Aware Test Data Compression Using Dictionary Based Coding","authors":"R. Karmakar, S. Chattopadhyay","doi":"10.1109/VLSID.2015.14","DOIUrl":"https://doi.org/10.1109/VLSID.2015.14","url":null,"abstract":"In this paper, we have proposed a new thermal-aware test data compression technique using dictionary based coding. Huge test data volume and chip temperature are two major challenges for test engineers. Temperature of a chip can be reduced to a large extent by minimizing transition count in scan chains using efficient don't-care filling. On the other hand, high compression ratio can be achieved by filling the don't-cares intelligently to get more similar sub-vectors from test vectors. Although, both of the problems rely on don't-care bit filling, most of the existing works have considered them as separate problems. In our work, we have combined both temperature reduction and compression into a single problem and solved it. We present an intermediate approach that performs a trade-off between temperature and compression ratio. Experimental results on ISCAS'89 and ITC'99 benchmarks show the flexibility of the proposed method to achieve a balance between temperature and compression ratio.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126582235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids","authors":"Nitin Salodkar, Subramanian Rajagopalan, S. Bhattacharya, S. Batterywala","doi":"10.1109/VLSID.2015.37","DOIUrl":"https://doi.org/10.1109/VLSID.2015.37","url":null,"abstract":"Traditionally, automatic design rule correction (DRC) problem is modeled as a linear program with technology rules and design intents modeled as difference constraints under a minimum perturbation objective. However, these linear programs are often infeasible due to conflicts arising from rules and intents, lack of space or due to incomplete modeling. It is then required to identify problematic constraints and either dilute or drop them to make the linear program feasible. In presence of uniform grid and only difference type constraints, a weighted constraint graph is constructed and infeasibilities are detected as positive cycles. However, this approach breaks down in presence of multiple layer specific grids or discrete track patterns. In this paper, we suggest a novel method for Infeasible Constraint Set Identification (ICSI) for such layouts. Our method transforms the constraint set into a Boolean implications set. Since each implication has only two variables, solving the ICSI problem amounts to determining 2-Satisfiability of the implications set. We then suggest various strategies to resolve infeasibilities.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125889183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Recessed MOSFET in 28 nm FDSOI for Better Breakdown Characteristics","authors":"N. K. Kranthi, R. Sithanandam, R. Komaragiri","doi":"10.1109/VLSID.2015.54","DOIUrl":"https://doi.org/10.1109/VLSID.2015.54","url":null,"abstract":"In this work, a novel recessed structure is proposed which improves the electric field distributions at the drain channel junction, hence the breakdown voltage. Technology computer aided design simulation results showed that the off state breakdown voltage of a 28 nm Fully Depleted Silicon on Insulator MOSFET is extended from 1.8V to 3.3 V or more. A detailed study is presented on the breakdown and DC characteristics of the same device. An asymmetric version of the same is also studied to further enhance the breakdown voltage and DC characteristics with and without Ground Plane (GP).","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"292 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114495977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures","authors":"Karthik Swaminathan, Jagadish B. Kotra, Huichu Liu, J. Sampson, M. Kandemir, N. Vijaykrishnan","doi":"10.1109/VLSID.2015.43","DOIUrl":"https://doi.org/10.1109/VLSID.2015.43","url":null,"abstract":"The challenges of the Power Wall manifest in mobile and embedded processors due to their inherent thermal and formfactor constraints. The power dissipated over a fixed area, namely, the power density, directly affects acceptable core temperatures even for low-power devices. In this paper, we examine techniques to counter this power density increase with device and microarchitecture-level heterogeneity. We explore the design space in which various parameters such as frequency and microarchitectural complexity can be traded off against each other in order to achieve the optimal configuration for a fixed temperature limit. Since conventional CMOS technology based cores may not satisfy our performance and power requirements, especially under tight thermal constraints, we propose a heterogeneous CMOS-Tunnel FET multicore for obtaining the optimal operating points under power and thermal limitations. Using a profiling based static assignment scheme, we demonstrate the improvement obtained by coupling this device-level heterogeneity to architectural modifications. We also propose an instruction slack-based scheme to map applications on the heterogeneous multicore. Our schemes show an improvement of up to 47% performance and 30% energy above the best homogeneous configuration.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115282900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}