2015 28th International Conference on VLSI Design最新文献

{"title":"On-the-Fly Donut Formation in Compiled Memory","authors":"Darvinder Singh, Isha Garg, Vineet Sachan, Prasanna Nalawar","doi":"10.1109/VLSID.2015.32","DOIUrl":"https://doi.org/10.1109/VLSID.2015.32","url":null,"abstract":"Timing data collection through memory compiler characterization is an integral part of memory compiler development. Simulations are run on an exhaustive instances list to cover the whole compiler range. Full characterization taxes resources immensely, both in terms of time and disk space. This paper focusses on on-the-fly donut creation methodology for the target memory compiler instance. In donut creation flow, nontiming critical bit cells are removed from the bit cell array while timing-critical bit cells are preserved. For an 80kB memory instance with close to 5 million transistors, RC extraction was not feasible using normal simulation machines. Comprehensive analysis, which earlier was impractical due to the difficulty of extracting the biggest (80kB) instance, was completed with the help of donut generation. Using on-the-fly donut formation flow, RC extracted net list was reduced by 75% and accuracy of timing simulations increased within 2%.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115436174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Exploring Scope of Power Reduction with Constrained Physical Synthesis","authors":"Kaustav Guha, Sourav Saha, R. Nigaglioni","doi":"10.1109/VLSID.2015.44","DOIUrl":"https://doi.org/10.1109/VLSID.2015.44","url":null,"abstract":"A new power optimization perspective based on constraint based library access in physical synthesis is presented in this paper. Power constraints are modelled and applied at the terminals of designs or sub designs based on relative power criticality of terminals. These constraints are then used in Physical Synthesis to selectively mask or expose different drive strength or threshold voltage variants of a given cell type. This constrained library access approach is compared with regular library access approach using a state-of-the-art power optimization engine. Experimental data shows it is possible to claim additional power savings in proposed approach with no or minimal performance impact. Also, it is possible to modulate this methodology to have selective focus on dynamic or leakage power if necessary.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"356 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122803765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Rectilinear Steiner Clock Tree Routing Technique with Buffer Insertion in Presence of Obstacles","authors":"Partha Pratim Saha, Sumonto Saha, T. Samanta","doi":"10.1109/VLSID.2015.81","DOIUrl":"https://doi.org/10.1109/VLSID.2015.81","url":null,"abstract":"Clock tree design plays a significant role in determining chip performance and requires serious involvement for designing a critical VLSI circuit. Algorithms to design clocked net involve complexities of memory and time along with the physical design constraints. In this work an efficient algorithm, BBLUE (Blockage Look Up and Buffer Estimation) is designed, which routes all the sinks in two phases. First routing in the global domain is achieved after tiling process and then routing in the local domain is done by connecting all the sinks inside a tile and combining the routes of all the tiles. Further in this work, BBLUE avoids the obstacles by snaking of wire with Steiner point insertion and the skew minimization is achieved by restricted buffer insertion in an efficient way. BBLUE is tested on ISPD 2010 benchmark suite and performance wise it is a better performer in certain parameters compared to its contenders of the benchmark suite provided by Intel and IBM.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123848179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Any Capacitor Stable LVR Using Sub-unity Gain Positive Feedback Loop in 65nm CMOS","authors":"S. Singh, N. Bansal","doi":"10.1109/VLSID.2015.50","DOIUrl":"https://doi.org/10.1109/VLSID.2015.50","url":null,"abstract":"In this paper a fully on-chip, any capacitor stable linear voltage regulator (LVR) using sub-unity gain positive feedback loop and NMOS pass element is presented. Sub-unity gain of the loop decouples loop stability from output capacitance value thus realizing any capacitor stable regulator. Regulator is shown to be stable for wide range of output capacitance values from 1nF to 40μF. Regulator output settles i n 0.5μs with peak to peak voltage variation of 158mV for a load current step of 0 to 115mA in 0.14μs with 1nF output capacitance. Response becomes better for higher values of output capacitance. LVR generates 1.25V output from 1.6V input while using another 3.0V input supply and occupies 0.18mm2 in 65nm CMOS.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126825082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SPAA-Aware 2D Gaussian Smoothing Filter Design Using Efficient Approximation Techniques","authors":"Ankur Jaiswal, Bharat Garg, Vikas Kaushal, G. K. Sharma","doi":"10.1109/VLSID.2015.62","DOIUrl":"https://doi.org/10.1109/VLSID.2015.62","url":null,"abstract":"The limited battery lifetime and rapidly increasing functionality of portable multimedia devices demand energy-efficient designs. The filters employed mainly in these devices are based on Gaussian smoothing, which is slow and, severely affects the performance. In this paper, we propose a novel energy-efficient approximate 2D Gaussian smoothing filter (2D-GSF) architecture by exploiting \"nearest pixel approximation\" and rounding-off Gaussian kernel coefficients. The proposed architecture significantly improves Speed-Power-Area-Accuracy (SPAA) metrics in designing energy-efficient filters. The efficacy of the proposed approximate 2D-GSF is demonstrated on real application such as edge detection. The simulation results show 72%, 79% and 76% reduction in area, power and delay, respectively with acceptable 0.4dB loss in PSNR as compared to the well-known approximate 2D-GSF.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127191318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tutorial T5: High Performance Low Power Designs - Challenges and Best practices in Design, Verification and Test","authors":"Nagesh Tamarapalli, P. Vallur, Sachin Kulkarni","doi":"10.1109/VLSID.2015.113","DOIUrl":"https://doi.org/10.1109/VLSID.2015.113","url":null,"abstract":"Demand for highly mobile and lower form-factor designs is driving semiconductor industry towards lower and lower power envelopes even for complex SOCs. With performance targets being expected to grow with every advancement in process technology, it becomes very difficult to achieve low power targets especially with shrinking geometries resulting in more pronounced second order effects in devices and interconnect. This tutorial is intended to cover some key challenges and best practices of design, verification and test domains for high performance ICs in low power space. First section starts off by explaining the basic trade-off between performance and power followed by how margins are used in various phases of design and analysis for better predictability of silicon behavior. It then covers the need for custom designs which could impact time-to-market but cannot be avoided due to the tighter and tighter specs on power and performance with every technology shift. This section concludes by discussing the impacts of overdesign and how they can be alleviated with some good practices during design phase. Second section covers the challenges involved in SOC-level and system-level verification of such high-performance designs with increased percentage of mixed-signal IP in them. It talks about some specific IPs and how to handle complex interactions between analog and digital domains there. It then covers the trade-off seen between speed and accuracy and associated best practices; and also covers some other common challenges like port order mismatches, etc. The final section addresses the challenge of testing the high performance designs especially given the process and design variability. For a long time semiconductor yield has been limited by random particle based issues and accordingly testing was geared towards detecting such defects. However, at feature sizes 65nm and below and with increased shift towards squeezing performance and power, systematic and process variability issues have begun to contribute significantly towards the yield fallout. In keeping up with this, testing has to adapt to be able to identify good devices from bad or not-so-good devices in the presence of variability. This section, after quickly summarizing the fundamentals will address advanced topics such as power-aware, timing-aware and variability aware test techniques and on-chip test structures and techniques that can be used to predict correlation between speed and power of the designs. The proposed tutorial quickly touches upon the basics to be of interest to students, new engineers and managers but primarily focuses on covering the key challenges seen across the industry today in design, verification and test phases of complex high performance SOCs in low power space. Since it covers multiple domains, the content should be of interest to a wide range of students, scholars and engineers.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127581878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Few Good Frequencies for Power-Constrained Test","authors":"S. Gunasekar, V. Agrawal","doi":"10.1109/VLSID.2015.72","DOIUrl":"https://doi.org/10.1109/VLSID.2015.72","url":null,"abstract":"In the a periodic clock testing method, power is kept at the specified limit by stretching or contracting the clock periods according to circuit activity. As reported, the test time of power constrained test can be reduced by 40-50%. Considering the capability of the test equipment and simplicity of test program, the number of clock periods should be kept low. In this paper, we give algorithms to find the optimum clock periods. Using the well known relation that the test time equals total energy for the entire test divided by the average power, the kth-root solution maximizes the average power for k test clocks and given maximum power constraint. This solution uses a piece-wise linear approximation for the sorted pseudo-energy profile of test cycles obtained from power estimation and timing analysis tools. For small k, the kth-root solution is optimized by a numerically efficient locally exhaustive search (LES) algorithm. Results show that close to maximum attainable test time reduction is achievable by as few as four to ten selected clocks.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"120 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128490395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimized Logarithmic Barrel Shifter in Reversible Logic Synthesis","authors":"Sajib Kumar Mitra, A. Chowdhury","doi":"10.1109/VLSID.2015.80","DOIUrl":"https://doi.org/10.1109/VLSID.2015.80","url":null,"abstract":"Reversible logic attains the dominance in the realm of overwhelming research in logic synthesis and also has the significance in the context of quantum computing because of loss-less information processing. Due to low power dissipation, researchers are first designing smaller components with reversible gates, that eventually lead to design reversible computer. In this paper, we propose a robust architecture of logarithmic barrel shifter that performs bidirectional arithmetic and logical shifting, including rotate operation. Incorporating fault tolerance capability, the circuit is designed very efficiently that exhibits superior performance over state-of-the-art design methods in terms of minimum number of gates, garbage outputs, ancilla inputs, quantum cost, delay and others cost factors.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129114608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Statistical Analysis of 64Mb SRAM for Optimizing Yield and Write Performance","authors":"Gaurav Narang, Pragya Sharma, Mansi Jain, Anuj Grover","doi":"10.1109/VLSID.2015.75","DOIUrl":"https://doi.org/10.1109/VLSID.2015.75","url":null,"abstract":"SRAMs occupy more than 50% of die area in high performance SoCs. Device variations in advanced technology nodes limit SRAM cell performance and yield. Maximum write time defines performance limited yield for SRAMs. In this work, we estimate sensitivity of write time of a 6T SRAM cell to variations in different devices through Design of Experiments (DoE) method. We evaluate multiple write-time models and estimate variation in yield for given write time specification. This work enables a performance vs yield trade-off and formalizes a Design for Yield (DFY) analysis. We benchmark multiple yield models and show that nonlinear models for write time are more accurate. We also estimate minimum required write time for different yield targets. We find that to achieve a target yield of 99%, SRAM designer needs to budget a write time of 656 ps when designing a 64Mb SRAM in 65nm technology. For a target yield of 90% with 1Mb capacity, 573 ps write time is sufficient and is 12% faster.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"07 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129392892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Tutorial T3: Error Resilient Real-Time Embedded Systems: Computing, Communications and Control","authors":"J. Abraham, A. Chatterjee","doi":"10.1109/VLSID.2015.111","DOIUrl":"https://doi.org/10.1109/VLSID.2015.111","url":null,"abstract":"Real-time embedded systems encompassing computing, communications and control are pushed towards always operating close to their limits of performance under virtually all operating conditions, for reasons of maximizing throughput per watt or just throughput, making the hardware susceptible to transient errors and noise due to reduced operating margins. In addition, the effects of process variations, electrical degradation and thermal hot-spots introduce additional concerns compounding the overall error resilience problem. In this tutorial, we present key resilience issues with the digital and mixed-signal/RF processing, control and sensor subsystems of real-time embedded systems. First, failure mechanisms and associated fault models are discussed for both permanent failures as well as transient errors particularly in the light of the adaptive nature of such systems (vis.a. vis. low power operation). Next, off-line testing and diagnosis of digital, analog and mixed-signal/RF circuits and subsystems is discussed, covering both catastrophic defects as well as parametric failure conditions. Advanced methods for postmanufacture tuning of digital and analog/RF devices to maximize manufacturing yield and field reliability are presented. Issues related to testing and tuning of adaptive systems with analysis of test cases are also analyzed. Finally, we present on-line testing methods for robustness of the complete embedded system to transient errors and induced noise. Applications to linear as well as nonlinear control of such real-time systems are discussed. We use a robotic system with a video sensor to illustrate the core concepts.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"37 Suppl 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116790509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}