G. Heck, Leandro S. Heck, Ajay Singhvi, Matheus T. Moreira, P. Beerel, Ney Laert Vilar Calazans
{"title":"Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits","authors":"G. Heck, Leandro S. Heck, Ajay Singhvi, Matheus T. Moreira, P. Beerel, Ney Laert Vilar Calazans","doi":"10.1109/VLSID.2015.60","DOIUrl":"https://doi.org/10.1109/VLSID.2015.60","url":null,"abstract":"We present the design and analysis of three commonly used types of programmable delay elements suitable for use in 2-phase bundled-data asynchronous circuits. Our objective is to minimize power consumption and delay margins needed for correct operation under voltage scaling. We propose both circuit design and transistor sizing strategies to optimize these elements and discuss the relative trade-offs observed in a 65 nm bulk CMOS technology.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131923770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Monitoring AMS Simulation: From Assertions to Features","authors":"Antara Ain, P. Dasgupta","doi":"10.1109/VLSID.2015.78","DOIUrl":"https://doi.org/10.1109/VLSID.2015.78","url":null,"abstract":"The complexity of analog mixed-signal (AMS) designs motivates the designers to analyze these systems in terms of features, which can be defined as the characterizing behavioral attributes of the designs. The first step towards automating the evaluation of feature values is to express the feature definitions in a formal way, and then to evaluate them over behavioral signatures. In this paper we present a framework for evaluating feature values over standard simulation platforms. Case studies over several circuit families are presented to illustrate the proposed methodology.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130859910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Dusa, Samiyuktha Kalalii, P. Rajalakshmi, O. Rao
{"title":"Integrated 16-Channel Transmit and Receive Beamforming ASIC for Ultrasound Imaging","authors":"C. Dusa, Samiyuktha Kalalii, P. Rajalakshmi, O. Rao","doi":"10.1109/VLSID.2015.42","DOIUrl":"https://doi.org/10.1109/VLSID.2015.42","url":null,"abstract":"In commercial ultrasound systems, the multielement transducer array is connected to analog front end electronics using long-wire high voltage coaxial cables. This paper presents the circuit design of 16-channel Transmit (Tx) and Receive (Rx) beam forming ASIC (Application Specific Integrated Circuit) that can be integrated in ultrasound probe head which reduces the number of coaxial cables. The proposed modular design for programmable 16-channel transmit beam former operates at medical frequencies in pulse-echo mode and provides user control of transmit parameters such as transmit pulse length, pulse pattern, transmit frequency, and mode of excitation. The receive beam former implements delay and coherent sum of the digitized echoes from 16 adjacent transducer elements to form scan lines required for image reconstruction. The proposed architecture of the Rx beam former design provides great flexibility for beam forming, such as receive focusing with predetermined delay profile. Each transmit channel can be programmable to give a maximum delay of 163.85 s with 1.25 ns delay resolution. The proposed design implements dynamic receive focusing with minimum time delay resolution of 3.125 ns for 40 MHz input data rate. The proposed ASIC of integrated Tx and Rx beam former is implemented in UMC 130 nm technology using Synopsys ICC and Design Compiler. The implementation reports show that the area is 5.29 mm2, power dissipation is 38 mW.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125502442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimal Test Scheduling of Stacked Circuits under Various Hardware and Power Constraints","authors":"S. Millican, K. Saluja","doi":"10.1109/VLSID.2015.88","DOIUrl":"https://doi.org/10.1109/VLSID.2015.88","url":null,"abstract":"As Integrated Circuits (ICs) become more complex through smaller semiconductor feature sizes and higher performance requirements, the thorough testing of silicon devices is becoming a greater economic challenge. System-on-Chip (SoC) test schedules not only need to achieve the shortest possible test application time, they must also satisfy new design constraints which are increasing test scheduling complexity, such as device power. Although many past studies of SoC test scheduling have addressed individual issues during test, none have present a model of test scheduling that has allowed for many different constraints to be enforced at once. By presenting a test scheduling formulation that allows the enforcement of many separate power and hardware constraints, including issues of test pins, as well as allowing the use of modern Dynamic Voltage and Frequency Scaling (DVFS) hardware to further compact test schedules, this study provides a generalized test scheduling formulation that will not only allow the enforcement of multiple testing constraints but will also allow for the further compaction of test schedules and reduction of test cost.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124288390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Tutorial T8: Scheduling Issues in Embedded Real-Time Systems","authors":"P. Ramanathan","doi":"10.1109/VLSID.2015.116","DOIUrl":"https://doi.org/10.1109/VLSID.2015.116","url":null,"abstract":"Summary form only given. The correctness of most computations in an embedded real-time application depends not only on the logical value but also on the time at which the results are produced. Examples of such applications include automotive systems, process control applications, aerospace applications, multimedia streaming, etc. Since the mid-1970s, various algorithms have been developed to schedule their real-time tasks without violating their timing constraints. In recent years, it has become apparent that next generation of embedded real-time systems must also deal with additional challenges such as power and thermal management constraints of modern day integrated circuits (IC). In this tutorial, we will discuss several models of real-time applications, introduce the different notions of real-time guarantees, review of scheduling algorithms with different real-time guarantees for single and multi-core systems, including algorithms that deal with emerging challenges such as processor's power and thermal constraints.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117354919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Prabhakar, Ujwal Mysore, Uday Saini, K. Vinoy, Bharadwaj Amruthur
{"title":"NFC for Pervasive Healthcare Monitoring","authors":"T. Prabhakar, Ujwal Mysore, Uday Saini, K. Vinoy, Bharadwaj Amruthur","doi":"10.1109/VLSID.2015.18","DOIUrl":"https://doi.org/10.1109/VLSID.2015.18","url":null,"abstract":"We undertake a step-by-step approach in the design of two Near Field Communication (NFC) products for pervasive healthcare monitoring. Our first product is an NFC based battery charger circuit to charge a thermometer equipped with wireless communication. Our system design has a simple linear charger, with overvoltage and under voltage protection implemented as an android App. The NFC power source provides 13 -- 15 mW of continuous power and is able to charge a 45mAH battery in about 10 hours from deep discharge to full charge state. Since the weight of the charger is about 3 grams and the size is about 2 cms in diameter, this product is useful for wearable sensor devices and provides a convenient way of recharging the batteries without the need for any connectors in the device. This allows devices to be hermetically sealed, besides enabling smaller form factors. The second product is an NFC based battery-less medical grade thermometer. To obtain the temperature of a single patient, a maximum of 10 seconds is sufficient to read the sensor value starting from placement of a smartphone over the product.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129023463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Anjan Kumar, Abhinav Dikshit, Bill Clark, Jeff Yan
{"title":"A Frequency Scan Scheme for PLL-Based Locking to High-Q MEMS Resonators","authors":"Anjan Kumar, Abhinav Dikshit, Bill Clark, Jeff Yan","doi":"10.1109/VLSID.2015.17","DOIUrl":"https://doi.org/10.1109/VLSID.2015.17","url":null,"abstract":"Making a MEMS resonator to oscillate at its natural frequency is an essential function in vibratory gyroscopes and is done by using a PLL inside the feedback loop. In particular, because of high Q (quality factor) resonators, signal levels at start up can be very low, posing challenges to achieve PLL lock or lead to unacceptable lock times. This paper proposes a novel frequency scan technique to achieve start up and, hence, lock for the loop. The paper describes a comparator circuit to convert the input sinusoid to a clock with in-built band pass filter, dc and ac hysteresis. Also a scheme is proposed to avoid wrong phase at start up which could arise in a resonator loop using charge pump based PLL. All the above techniques are implemented in TSMC 0.18 micron process for the ADXRS290 gyroscope product and results show a reliable PLL lock with startup time <;5 ms for up to a Q of 2500.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115814538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sivaramakrishna Rudrapati, Sharayu Jagtap, M. U. Shaikh, Shalabh Gupta
{"title":"A Wide Tuning Range LC Quadrature Phase Oscillator Employing Mode Switching","authors":"Sivaramakrishna Rudrapati, Sharayu Jagtap, M. U. Shaikh, Shalabh Gupta","doi":"10.1109/VLSID.2015.52","DOIUrl":"https://doi.org/10.1109/VLSID.2015.52","url":null,"abstract":"We present a wide tuning range quadrature phase LC oscillator in this paper. A combination of series-coupled and parallel-coupled topologies between the two LC tanks in the oscillator is used. Series-coupled topology ensures that a desired phase sequence is achieved, whereas, tunability and switching of parallel-coupling helps in achieving very wide tuning range. Furthermore, use of varactors, which are unsuitable for high frequencies because of their losses, is avoided as significant frequency tuning can be achieved by varying the coupling strength itself. Circuit simulation results show that an 11 GHz oscillator, designed in a standard 90 nm CMOS technology in this topology, achieves a tuning range of more than 46%.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116064254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On Slew Rate Enhancement in Class-A Opamps Using Local Common-Mode Feedback","authors":"K. S. Rakshitdatta, N. Krishnapura","doi":"10.1109/VLSID.2015.47","DOIUrl":"https://doi.org/10.1109/VLSID.2015.47","url":null,"abstract":"The output common-mode voltage in multistage fully differential opamps can be set by using a single common-mode feedback loop around all stages or by independent loops for each stage. The two schemes are analyzed for their impact on the slew rate in a two-stage Miller-compensated class-A opamp. Analysis and simulation results show that using local common-mode feedback loops will lead to higher slew rate. This is because, when slewing, both upper and lower transistors receive signal dependent gate voltages with local common-mode feedback, making the behavior similar to that of a class-AB output stage. Also, with local common-mode feedback, the positive and negative slew rates are symmetric.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128643431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 300 KBPS 23.2 MHz Binary Frequency Shift Keying Transmitter for USB Power Line Communication in 180 nm BiCMOS","authors":"A. S. Rao, Karthik Subburaj","doi":"10.1109/VLSID.2015.89","DOIUrl":"https://doi.org/10.1109/VLSID.2015.89","url":null,"abstract":"A Binary Frequency Shift Keying transmitter particularly suited for the recently introduced USB Power Delivery standard is presented here. The proposed architecture uses a combination of intelligent frequency planning, an unmodulated high frequency PLL, a digital clock rate converter, and a sine-weighted DAC impedance matched to the power-line network. This combination simultaneously achieves frequency keying and output signal generation in a novel highly integrated way. It achieves a Figure of Merit and a data-rate-normalized energy efficiency better than or comparable to generic Direct Digital Synthesis architectures and previously published FSK designs, at a fraction of their die area. Details of its architecture and implementation, 180 nm BiCMOS measurement results, and comparison with best existing designs are presented.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132861567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}