A 300 KBPS 23.2 MHz Binary Frequency Shift Keying Transmitter for USB Power Line Communication in 180 nm BiCMOS

Abstract

A Binary Frequency Shift Keying transmitter particularly suited for the recently introduced USB Power Delivery standard is presented here. The proposed architecture uses a combination of intelligent frequency planning, an unmodulated high frequency PLL, a digital clock rate converter, and a sine-weighted DAC impedance matched to the power-line network. This combination simultaneously achieves frequency keying and output signal generation in a novel highly integrated way. It achieves a Figure of Merit and a data-rate-normalized energy efficiency better than or comparable to generic Direct Digital Synthesis architectures and previously published FSK designs, at a fraction of their die area. Details of its architecture and implementation, 180 nm BiCMOS measurement results, and comparison with best existing designs are presented.