R. Ahmed, Ayoosh Bansal, Bhuvana Kakunoori, P. Ramanathan, K. Saluja
{"title":"Thermal Extension of the Total Bandwidth Server","authors":"R. Ahmed, Ayoosh Bansal, Bhuvana Kakunoori, P. Ramanathan, K. Saluja","doi":"10.1109/VLSID.2015.13","DOIUrl":"https://doi.org/10.1109/VLSID.2015.13","url":null,"abstract":"A typical real-time application is composed of periodic tasks with hard deadline constraints. It must also service a periodic tasks that are generated in response to external and internal events. In addition to application's timing constraints, it is important that the system never violates thermal constraint due to its increasingly adverse impact on the processing platform. In this work, we propose a scheme for servicing a periodic tasks in thermally constrained hard real-time systems. We propose an algorithm, T2BS, which is a thermal extension of the Total Bandwidth Server [1]. We show that our algorithm is optimal in the sense that it meets periodic task timing constraints as well as system thermal constraints, and it supports the maximum rate of a periodic arrivals. Through extensive simulations we demonstrate the validity of theoretical results and perform the response time analysis of a periodic tasks.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131361183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Sensitivity Analysis Based Predictive Modeling for MPSoC Performance and Energy Estimation","authors":"Hongwei Wang, Ziyuan Zhu, Jinglin Shi, Yongtao Su","doi":"10.1109/VLSID.2015.92","DOIUrl":"https://doi.org/10.1109/VLSID.2015.92","url":null,"abstract":"Multi-processor system on chip (MPSoC) has been a de facto standard for embedded processor architectures. However, the architectural design space of MPSoC is so huge that it is time prohibitive to exhaustively simulate all design points to evaluate their design metrics (such as performance, energy, etc.). Thus, many architects have resorted to predictive modeling methods to fast estimate the design metrics of design points. An essential task in these techniques is input variable selection. Input variables of the predictive model consist of architecture parameters and their interactions, but not all input variables should be included in model. The inclusion of significant input variables in model can improve the prediction accuracy of model, but the inclusion of insignificant input variables will increase the risk of over fitting. So, how to identify and include the significant input variables while exclude the insignificant ones is a great challenge. In this paper, we propose an adaptive component selection and smoothing operator (ACOSSO) regression technique for predictive modeling of MPSoC performance and energy. The ACOSSO regression technique allows simultaneous global sensitivity analysis (which performs input variable selection) and model computing through solving an L1-norm penalized least squares fitting problem. We compare the proposed ACOSSO model with the state-of-the-art restricted cubic splines (RCS) model and two enhanced RCS models by applying them to an MPSoC performance and energy estimation problem. One enhanced RCS model performs input variable selection by use of ACOSSO regression based sensitivity analysis technique and the other by a stepwise regression modeling technique. Experimental results show that the ACOSSO regression model has better prediction accuracy than the other models, and the results of ACOSSO regression based sensitivity analysis are also useful for RCS modeling.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133879810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On-the-Fly Mapping for Synthesizing Dynamic Domino Circuits","authors":"S. Kadiyala, D. Samanta","doi":"10.1109/VLSID.2015.83","DOIUrl":"https://doi.org/10.1109/VLSID.2015.83","url":null,"abstract":"In recent times, the usage of Domino logic in design of high performance circuits is increasing. In addition to its high performance advantage, the Domino logic style also offers flexibility in designing individual cells. Flexible height and width of cells gives the designer an advantage to realize a large variety of functions. This gives a scope for library free mapping. In this work, we present an approach for mapping a Domino logic circuit using on-the-fly technique. First, we present a node mapping algorithm which maps a given Domino logic net list using on-the-fly technique. Next, using an Equivalence Table, we re-order the cells along the critical path of the circuit for delay and area improvement. Finally, we find an optimum re-ordering set which can obtain maximum delay and area savings. We have tested the efficacy of our approach with a set of standard benchmark circuits. Our proposed mapping approach called Delay Area Aware Mapping (DAAM) obtained 21% improvement in area and 17% improvement in delay compared to the existing work.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128099841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Smart Port Allocation for Adaptive NoC Routers","authors":"R. James, John Jose, Jobin K. Antony","doi":"10.1109/VLSID.2015.86","DOIUrl":"https://doi.org/10.1109/VLSID.2015.86","url":null,"abstract":"Network on Chip (NoC) is an emerging communication framework for multiple processing cores on a System on Chip (SoC). The router micro-architecture determines the performance of such a communication network to a great extend. Considering the cost effective performance and scalability, minimally buffered deflection routers are emerging as a popular design choice for NoC based multicore systems. In this paper, a new router architecture is proposed which has an enhanced pipeline register and a smart port allocator that significantly reduces the pipeline stage delay in the router. The proposed smart port allocator assigns output port to incoming flits dynamically based on available output ports and flit occupancy level of the enhanced pipeline register. This eliminates unwanted intra-router movement of flits. Experimental results on synthetic and real workloads show that the proposed router reduces average packet latency, output channel wastage, deflection rate of flits and increases the throughput in the network when compared to the state-of-the-art minimally buffered deflection routers.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121737598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Accurate Constant Transconductance Generation without Off-Chip Components","authors":"Imon Mondal, N. Krishnapura","doi":"10.1109/VLSID.2015.48","DOIUrl":"https://doi.org/10.1109/VLSID.2015.48","url":null,"abstract":"A process, voltage, and temperature invariant transconductance generation technique without the use of any off-chip components is proposed. It generates transconductance by tracking an MOSFET in linear region, whose conductance is precisely controlled by negative feedback using constant voltage and current references. Simulation results of a prototype transconductor in 0.13μm CMOS technology show an inaccuracy of less than 0.5% for 120°C variation of temperature and a deviation of ±4 % with mismatch.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130031842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On Event Driven Modeling of Continuous Time Systems","authors":"Dushyant Juneja","doi":"10.1109/VLSID.2015.39","DOIUrl":"https://doi.org/10.1109/VLSID.2015.39","url":null,"abstract":"Factors such as expanding feature set and algorithmic designs drive modern SoCs towards larger and tightly coupled mixed signal content. Traditional digital HDLs and Verification oriented languages come forth to support this development by evolving with powerful mixed signal modeling facilities for early and improved verification of digital-analog (and vice-versa) interaction. Under such circumstances, it becomes essential for the AMS verification engineer to figure out ways for overcoming continuous time modeling challenges in the traditionally event driven digital simulators. The paper intends to highlight the endeavors and optimizations for such an effort, uncovering the aforesaid modeling technology's sweet spots, bottlenecks and abstraction requirements. Optimizations are discussed for the bottlenecks discovered, prominently continuous time filters and feedback circuits, and elaborations are presented on new simulation concerns such as numerical instability. Results are presented reasserting that while such a modeling approach can present almost 100x speed enhancement, it can also result in a severe speed penalty when misapplied (200x slower, here).","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125342406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Rahul, Bibhudatta Sahoo, S. Arya, S. Parvathy, Veeresh Babu Vulligaddala
{"title":"A Wide Dynamic-Range Low-Power Signal Conditioning Circuit for Low-Side Current Sensing Application","authors":"T. Rahul, Bibhudatta Sahoo, S. Arya, S. Parvathy, Veeresh Babu Vulligaddala","doi":"10.1109/VLSID.2015.51","DOIUrl":"https://doi.org/10.1109/VLSID.2015.51","url":null,"abstract":"This paper proposes a wide dynamic-range lowpower signal conditioning circuit for low-side current sensing application. The proposed architecture uses a double sampling technique for switched capacitor programmable gain amplifier (SC-PGA) thus enabling the PGA to work at low frequency However, the analog-to-digital converter (ADC), which digitizes the amplified signal works at high frequency to achieve high dynamic range. The double sampling technique relaxes the slewrate and settling requirement of the op amp in the PGA. The switched capacitor implementation obviates the need for explicit level-shifting circuit while enabling rail-to-rail input common mode. The closed loop SC-PGA architecture is very robust to gain drift due to temperature and supply voltage variation. The design incorporates correlated double sampling technique to overcome offset and flicker noise. The analog-to-digital converter used in this design is a multi-bit second order ΔΣ-ADC [14]. The circuit is implemented in AMS 0.35 μm CMOS process with 3.3 V supply. Simulations show that the overall system, i.e., PGA and ΔΣ-ADC, achieves a dynamic range in excess of 80 dB while consuming 2 mA.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131613970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Naman Maheshwari, Zhixi Yang, Jie Han, F. Lombardi
{"title":"A Design Approach for Compressor Based Approximate Multipliers","authors":"Naman Maheshwari, Zhixi Yang, Jie Han, F. Lombardi","doi":"10.1109/VLSID.2015.41","DOIUrl":"https://doi.org/10.1109/VLSID.2015.41","url":null,"abstract":"Approximate computing is best suited for error resilient applications, such as signal processing and multimedia. Approximate computing reduces accuracy, but it still provides meaningful and faster results with usually lower power consumption, this is particularly attractive for arithmetic circuits. In this paper, a new design approach is proposed to exploit the partitions of partial products using recursive multiplication for compressor-based approximate multipliers. Four multiplier designs are proposed using 4:2 approximate compressors. Extensive simulation results show that the proposed designs achieve significant accuracy improvement together with power and delay reductions compared to previous approximate designs. An image processing application is also presented to show the efficiency of the proposed designs.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123657746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Comparison of Off-Chip Training Methods for Neuromemristive Systems","authors":"Cory E. Merkel, D. Kudithipudi","doi":"10.1109/VLSID.2015.22","DOIUrl":"https://doi.org/10.1109/VLSID.2015.22","url":null,"abstract":"Neuromemristive systems offer an efficient platform for learning and modeling non-linear functions in real time. Specifically, they are effective tools for pattern classification. However, training these systems presents several challenges, especially when CMOS and memristor process variations are considered. In this paper, we propose two off-chip training methods for neuromemristive systems: weight programming and feature training. Detailed variation models are developed to study the effects of CMOS and memristor process variations on neuromemristive circuits, including neurons, synapses, and training circuits. We analyze the impact of those variations on the proposed off-chip training methods. Specifically, we train a neuromemristive system to classify handwritten digits. The results indicate that the feature training method is able to provide over 2× better classification accuracy per unit area than the weight programming method. However, the weight programming method is much faster, and may be more suitable when the network needs to be frequently re-trained.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129760529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Novel CKE-ODT-CSN Encoding Scheme in DDR Memory Interface","authors":"V. Murugan, Narayanan Mayandi, A. Sendhil","doi":"10.1109/VLSID.2015.40","DOIUrl":"https://doi.org/10.1109/VLSID.2015.40","url":null,"abstract":"In the continuous evolution of DRAM technologies and increased pin count, the paper outlines the roadblocks faced in adding new pins and presents a novel coding approach for elimination of pins in DDR memory interface. The paper targets CSN, CKE and ODT pins of DRAM and presents a coding algorithm where all the mentioned pins' information is encoded and transferred to the DRAM on only two pins against the original three. The encoding and decoding blocks are discussed across both single data rate and double data rate DDR CA topology. The paper concludes by explaining the importance of the encoding algorithm and the additional features which can be supported through the coding scheme.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133248888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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