Smart Port Allocation for Adaptive NoC Routers

Abstract

Network on Chip (NoC) is an emerging communication framework for multiple processing cores on a System on Chip (SoC). The router micro-architecture determines the performance of such a communication network to a great extend. Considering the cost effective performance and scalability, minimally buffered deflection routers are emerging as a popular design choice for NoC based multicore systems. In this paper, a new router architecture is proposed which has an enhanced pipeline register and a smart port allocator that significantly reduces the pipeline stage delay in the router. The proposed smart port allocator assigns output port to incoming flits dynamically based on available output ports and flit occupancy level of the enhanced pipeline register. This eliminates unwanted intra-router movement of flits. Experimental results on synthetic and real workloads show that the proposed router reduces average packet latency, output channel wastage, deflection rate of flits and increases the throughput in the network when compared to the state-of-the-art minimally buffered deflection routers.