Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits

G. Heck, Leandro S. Heck, Ajay Singhvi, Matheus T. Moreira, P. Beerel, Ney Laert Vilar Calazans
{"title":"Analysis and Optimization of Programmable Delay Elements for 2-Phase Bundled-Data Circuits","authors":"G. Heck, Leandro S. Heck, Ajay Singhvi, Matheus T. Moreira, P. Beerel, Ney Laert Vilar Calazans","doi":"10.1109/VLSID.2015.60","DOIUrl":null,"url":null,"abstract":"We present the design and analysis of three commonly used types of programmable delay elements suitable for use in 2-phase bundled-data asynchronous circuits. Our objective is to minimize power consumption and delay margins needed for correct operation under voltage scaling. We propose both circuit design and transistor sizing strategies to optimize these elements and discuss the relative trade-offs observed in a 65 nm bulk CMOS technology.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 28th International Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSID.2015.60","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 18

Abstract

We present the design and analysis of three commonly used types of programmable delay elements suitable for use in 2-phase bundled-data asynchronous circuits. Our objective is to minimize power consumption and delay margins needed for correct operation under voltage scaling. We propose both circuit design and transistor sizing strategies to optimize these elements and discuss the relative trade-offs observed in a 65 nm bulk CMOS technology.
两相捆绑数据电路中可编程延迟元件的分析与优化
我们提出了三种常用的可编程延迟元件的设计和分析,适用于两相捆绑数据异步电路。我们的目标是尽量减少在电压缩放下正确操作所需的功耗和延迟余量。我们提出了电路设计和晶体管尺寸策略来优化这些元件,并讨论了在65nm块体CMOS技术中观察到的相关权衡。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
求助全文
约1分钟内获得全文 求助全文
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信