2015 28th International Conference on VLSI Design最新文献_第3页

Embedded Tutorial ET2: Volume Diagnosis for Yield Improvement 嵌入式教程ET2:产量改进的体积诊断

2015 28th International Conference on VLSI Design Pub Date : 2015-02-05 DOI: 10.1109/VLSID.2015.119

Wu-Tung Cheng, S. Reddy

引用次数: 1

All Optical Implementation of Mach-Zehnder Interferometer Based Reversible Sequential Counters 基于可逆顺序计数器的Mach-Zehnder干涉仪全光学实现

2015 28th International Conference on VLSI Design Pub Date : 2015-02-05 DOI: 10.1109/VLSID.2015.45

Pratik Dutta, Chandan Bandyopadhyay, H. Rahaman

引用次数: 8

Can You Trust Your Memory Trace? A Comparison of Memory Traces from Binary Instrumentation and Simulation 你能相信你的记忆痕迹吗?二进制仪器与仿真的内存轨迹比较

2015 28th International Conference on VLSI Design Pub Date : 2015-02-05 DOI: 10.1109/VLSID.2015.28

Siddharth Nilakantan, Scott Lerner, Mark Hempstead, B. Taskin

{"title":"Can You Trust Your Memory Trace? A Comparison of Memory Traces from Binary Instrumentation and Simulation","authors":"Siddharth Nilakantan, Scott Lerner, Mark Hempstead, B. Taskin","doi":"10.1109/VLSID.2015.28","DOIUrl":"https://doi.org/10.1109/VLSID.2015.28","url":null,"abstract":"Simulation is employed extensively to perform exploration of design spaces by computer designers. Contemporary simulation environments are now increasingly complex comprising of support for multiple cores and full operating systems. Resource use between simulation environments vary widely because of these different system contexts and the fact that multi-threaded applications have intrinsic non-determinism. In addition, more recent simulation environments use Dynamic Binary Instrumentation (DBI) traces collected on the system context (OS, library, threading API) of the host system. Methodologies that have been employed to validate and compare simulation frameworks are usually limited to comparing CPI and cache statistics and do not provide a detailed function-level breakdown or understanding of the source of mismatches. In this work, we attempt to identify and quantify the true sources of mismatch between a DBI framework and a full system simulation framework. We use memory traces of multithreaded applications that have been annotated with function call information to allow for a breakdown of the source of mismatch within an application. To the best of our knowledge, this level of detail in comparison has not been attempted before, especially with traces of multi-threaded applications. In this study, we find that the sources of mismatch come mainly from threading mechanisms/threading API function calls, Library/System function calls and User Space condition synchronization. Based on the results of the study, we identify specific functions in each category of mismatch. We then propose a few ways to close the gap and enable more reliable simulation for design space exploration.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122078293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Towards a Real-Time Campus-Scale Water Balance Monitoring System 校园水平衡实时监测系统的实现

2015 28th International Conference on VLSI Design Pub Date : 2015-02-05 DOI: 10.1109/VLSID.2015.20

Vignesh D. Kudva, P. Nayak, Alok Rawat, Anjana G. Ry, K. R. S. Kumar, B. Amrutur, Mohan Kumar M. Sy

引用次数: 12

Reliability Enhancement of SoCs Based on Dynamic Memory Access Profiling in Conjunction with PVT Monitoring 基于动态内存访问分析和PVT监测的soc可靠性增强

2015 28th International Conference on VLSI Design Pub Date : 2015-02-05 DOI: 10.1109/VLSID.2015.97

Deepak Baranwal, Digvijay Singh, Khanusiya Soyeb, Sidhartha Sankar Rout, Sujay Deb

{"title":"Reliability Enhancement of SoCs Based on Dynamic Memory Access Profiling in Conjunction with PVT Monitoring","authors":"Deepak Baranwal, Digvijay Singh, Khanusiya Soyeb, Sidhartha Sankar Rout, Sujay Deb","doi":"10.1109/VLSID.2015.97","DOIUrl":"https://doi.org/10.1109/VLSID.2015.97","url":null,"abstract":"The growing technology scaling and larger die size of multi-processor System-On-Chip have increased the error rates for on-chip memories. Increased system speed for high performance, aggressive voltages scaling for power reduction and intra-die process variation have exaggerated the unreliability issue. In this paper a method for memory management on SoCs to enhance their reliability is discussed. The method consists of a mechanism for automatically moving the contents of a less reliable memory to a more reliable memory. The solution module designed as RAIMM (Reliability Aware Intelligent Memory Management) is an architectural framework to dynamically compute reliability of the on-chip memories and provide a better reliable solution for the application in case of any memory failure. The silicon characterization data is used in conjunction with the on-chip process/voltage/temperature sensors to correctly estimate the memory reliability status. It provides a ranking mechanism for the available memories based on the operating conditions, silicon characterization data as well as dynamic access profiling data, which can be used to provide a method to accurately predict memory failure in advance to the application. An efficiently hardware programmed Direct Memory Access (DMA) engine ensures the efficient working of overall application with low overhead for software in maintaining the memory configuration and contents.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131637600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Geometric Programming Formulation for Gate Sizing with Pipelining Constraints 具有流水线约束的浇口尺寸几何规划公式

2015 28th International Conference on VLSI Design Pub Date : 2015-02-05 DOI: 10.1109/VLSID.2015.82

S. Naidu

引用次数: 4

Noninvasive cuffless blood pressure measurement by vascular transit time 血管传递时间无创无袖带血压测量

2015 28th International Conference on VLSI Design Pub Date : 2015-02-05 DOI: 10.1109/VLSID.2015.96

Satya Narayan Shukla, Karan Kakwani, A. Patra, Bipin Kumar Lahkar, V MNSSVKR GUPTA, Alwar Jayakrishna, Puneet Vashisht, Induja Sreekanth

{"title":"Noninvasive cuffless blood pressure measurement by vascular transit time","authors":"Satya Narayan Shukla, Karan Kakwani, A. Patra, Bipin Kumar Lahkar, V MNSSVKR GUPTA, Alwar Jayakrishna, Puneet Vashisht, Induja Sreekanth","doi":"10.1109/VLSID.2015.96","DOIUrl":"https://doi.org/10.1109/VLSID.2015.96","url":null,"abstract":"Blood pressure (BP) is one of the most important physiological parameters that can provide valuable information for personal health care. There are two ways to measure human blood pressure viz. Invasive and noninvasive methods. Though invasive methods have been known to measure BP continuously and accurately but they are extremely inconvenient to use and might cause infection. The widely used cuff-based noninvasive methods are also not very convenient to use especially for injured or obese people and infants. Thus, there has been an unmet need for a convenient noninvasive cuff less BP measurement technique. While cuff less methods to measure BP have been previously studied, most of them were limited to offline processing of captured signals and none have presented an end-to-end prototype. Therefore, in this paper, we present a simple and low-cost fully realized implementation that can measure Blood Pressure immediately after capturing heart activity signals from a user namely PPG (Photo plethysmograph) and PCG (Phonocardiogram). The data is transmitted through a Bluetooth module in the system and results are displayed in a user interactive android application. We compared our results with those measured using a commercial cuff-based digital blood pressure measuring device and obtained encouraging results of about 95% accuracy.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131034690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 21

DyMeP: An Infrastructure to Support Dynamic Memory Binding for Runtime Mapping in CGRAs 支持CGRAs中运行时映射的动态内存绑定的基础结构

2015 28th International Conference on VLSI Design Pub Date : 2015-02-05 DOI: 10.1109/VLSID.2015.98

Muhammad Adeel Tajammul, Syed M. A. H. Jafri, P. Ellervee, A. Hemani, H. Tenhunen, J. Plosila

{"title":"DyMeP: An Infrastructure to Support Dynamic Memory Binding for Runtime Mapping in CGRAs","authors":"Muhammad Adeel Tajammul, Syed M. A. H. Jafri, P. Ellervee, A. Hemani, H. Tenhunen, J. Plosila","doi":"10.1109/VLSID.2015.98","DOIUrl":"https://doi.org/10.1109/VLSID.2015.98","url":null,"abstract":"Coarse Grained Reconfigurable Architectures (CGRAs) are emerging as enabling platforms to meet the high performance demanded by modern applications. Commonly, CGRAs are composed of a computation layer (that performs computations) and a memory layer (that provides data and config ware to the computation layer). Tempted by higher platform utilization and reliability, recently proposed CGRA soffer dynamic application remapping (for the computation layer). Distributed scratch pad (compiler programmed) memories offer high data rates, predictability and low the power consumption (compared to caches). Therefore, the distributed scratchpad memories are emerging as preferred implementation alternative for the memory layer in recent CGRAs. However, the scratchpad memories are programmed at compile time, and do not support dynamic application remapping. The existing solutions that allow dynamic application remapping either rely on fat binaries (that significantly enhance configuration memory requirements) or consider a centralized memory. To extract the benefits of both runtime remapping and distributed scratchpad memories, we present a design framework called DyMeP. DyMeP relies on late binding and provides the architectural support to dynamically remap data in CGRAs. Compared to the state of the art, the proposed technique reduces the configuration memory requirements (needed by fat binary solutions) and supports distributed shared scratchpad memory. Synthesis/Simulation results reveal that DyMeP promises a significant (up to 60%) reduction in config ware size at the cost of negligible additional overheads (less then 1%).","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128543008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Design of 3D Antennas for 24 GHz ISM Band Applications 24ghz ISM波段应用的3D天线设计

2015 28th International Conference on VLSI Design Pub Date : 2015-02-05 DOI: 10.1109/VLSID.2015.85

P. Sravani, M. Rao

{"title":"Design of 3D Antennas for 24 GHz ISM Band Applications","authors":"P. Sravani, M. Rao","doi":"10.1109/VLSID.2015.85","DOIUrl":"https://doi.org/10.1109/VLSID.2015.85","url":null,"abstract":"A novel three dimensional (3D) antenna is designed for 24 GHz frequency ISM band applications. The 3D antenna uses optimal 2D space and relies heavily on 3D structures to provide improved antenna performance. Four different 3D antenna configurations are studied to understand the improvement in the antenna design. The antenna parameters and surface current distribution are compared with patch antenna of 24 GHz frequency. The 3D configuration allows more space for device fabrication and enhance the chip functionalities. The 3D architecture consist of antenna, which is fed by quarter wave transmission line to match antenna impedance. A wave port is designed to characterize the antenna. The designed 3D antenna is compact as compared to 2D planar patch antenna of same frequency. In the 3D architecture, the current is distributed to the patch on a different plane via 3D conducting channels. The current distribution shows maximum current in the surface conducting layer for two types of the 3D antenna designed. The compact 3D antenna is designed to radiate at 24 GHz and occupies space of less than 3.75 mm × 3.75 mm in the die as compared to the space of 7.27 mm × 7.27 mm for planar patch antenna of similar frequency. The reduction in space offers wide advantages in designing on-chip RF systems. The simulation of the antennas were completed using An soft HFSS™, 3D electromagnetic tool.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133289075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Tutorial T1: Neuromorphic Computing - Algorithms, Devices and Systems 教程T1:神经形态计算-算法，设备和系统

2015 28th International Conference on VLSI Design Pub Date : 2015-02-05 DOI: 10.1109/VLSID.2015.109

B. Rajendran, U. Ganguly, M. Suri

引用次数: 1