{"title":"具有流水线约束的浇口尺寸几何规划公式","authors":"S. Naidu","doi":"10.1109/VLSID.2015.82","DOIUrl":null,"url":null,"abstract":"We propose a novel framework to solve the combined retiming/gate sizing problem in the context of optimization of acyclic pipelines. The adjustment of sizes to gates in a combinational circuit is a continuous problem, solvable by a variety of convex optimization tools provided the delay model for each gate is placed in a convex framework. Retiming is a discrete problem since it involves physically moving registers from one location to another. In this paper, we enhance an existing convex optimization framework proposed by Boyd et al [1] to handle registers as 0-1 variables. We solve the relaxed formulation as a geometric program and glean valuable information about the circuit's performance. Another significant contribution of our paper is that we show that our problem is NP-hard.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Geometric Programming Formulation for Gate Sizing with Pipelining Constraints\",\"authors\":\"S. Naidu\",\"doi\":\"10.1109/VLSID.2015.82\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose a novel framework to solve the combined retiming/gate sizing problem in the context of optimization of acyclic pipelines. The adjustment of sizes to gates in a combinational circuit is a continuous problem, solvable by a variety of convex optimization tools provided the delay model for each gate is placed in a convex framework. Retiming is a discrete problem since it involves physically moving registers from one location to another. In this paper, we enhance an existing convex optimization framework proposed by Boyd et al [1] to handle registers as 0-1 variables. We solve the relaxed formulation as a geometric program and glean valuable information about the circuit's performance. Another significant contribution of our paper is that we show that our problem is NP-hard.\",\"PeriodicalId\":123635,\"journal\":{\"name\":\"2015 28th International Conference on VLSI Design\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-02-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 28th International Conference on VLSI Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSID.2015.82\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 28th International Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSID.2015.82","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Geometric Programming Formulation for Gate Sizing with Pipelining Constraints
We propose a novel framework to solve the combined retiming/gate sizing problem in the context of optimization of acyclic pipelines. The adjustment of sizes to gates in a combinational circuit is a continuous problem, solvable by a variety of convex optimization tools provided the delay model for each gate is placed in a convex framework. Retiming is a discrete problem since it involves physically moving registers from one location to another. In this paper, we enhance an existing convex optimization framework proposed by Boyd et al [1] to handle registers as 0-1 variables. We solve the relaxed formulation as a geometric program and glean valuable information about the circuit's performance. Another significant contribution of our paper is that we show that our problem is NP-hard.