Nagesh Tamarapalli, P. Vallur, Sachin Kulkarni
{"title":"Tutorial T5: High Performance Low Power Designs - Challenges and Best practices in Design, Verification and Test","authors":"Nagesh Tamarapalli, P. Vallur, Sachin Kulkarni","doi":"10.1109/VLSID.2015.113","DOIUrl":null,"url":null,"abstract":"Demand for highly mobile and lower form-factor designs is driving semiconductor industry towards lower and lower power envelopes even for complex SOCs. With performance targets being expected to grow with every advancement in process technology, it becomes very difficult to achieve low power targets especially with shrinking geometries resulting in more pronounced second order effects in devices and interconnect. This tutorial is intended to cover some key challenges and best practices of design, verification and test domains for high performance ICs in low power space. First section starts off by explaining the basic trade-off between performance and power followed by how margins are used in various phases of design and analysis for better predictability of silicon behavior. It then covers the need for custom designs which could impact time-to-market but cannot be avoided due to the tighter and tighter specs on power and performance with every technology shift. This section concludes by discussing the impacts of overdesign and how they can be alleviated with some good practices during design phase. Second section covers the challenges involved in SOC-level and system-level verification of such high-performance designs with increased percentage of mixed-signal IP in them. It talks about some specific IPs and how to handle complex interactions between analog and digital domains there. It then covers the trade-off seen between speed and accuracy and associated best practices; and also covers some other common challenges like port order mismatches, etc. The final section addresses the challenge of testing the high performance designs especially given the process and design variability. For a long time semiconductor yield has been limited by random particle based issues and accordingly testing was geared towards detecting such defects. However, at feature sizes 65nm and below and with increased shift towards squeezing performance and power, systematic and process variability issues have begun to contribute significantly towards the yield fallout. In keeping up with this, testing has to adapt to be able to identify good devices from bad or not-so-good devices in the presence of variability. This section, after quickly summarizing the fundamentals will address advanced topics such as power-aware, timing-aware and variability aware test techniques and on-chip test structures and techniques that can be used to predict correlation between speed and power of the designs. The proposed tutorial quickly touches upon the basics to be of interest to students, new engineers and managers but primarily focuses on covering the key challenges seen across the industry today in design, verification and test phases of complex high performance SOCs in low power space. Since it covers multiple domains, the content should be of interest to a wide range of students, scholars and engineers.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"116 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 28th International Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSID.2015.113","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

对高移动性和低外形尺寸设计的需求正在推动半导体行业朝着更低功耗的方向发展,即使对于复杂的soc也是如此。随着工艺技术的每一次进步,性能目标都有望增长,实现低功耗目标变得非常困难,特别是由于几何形状的缩小,导致器件和互连中的二阶效应更加明显。本教程旨在介绍低功耗高性能ic设计、验证和测试领域的一些关键挑战和最佳实践。第一部分首先解释性能和功耗之间的基本权衡,然后是如何在设计和分析的各个阶段使用余量,以更好地预测硅的行为。然后,它涵盖了定制设计的需求,这可能会影响上市时间,但由于每次技术转变对功率和性能的要求越来越严格,因此无法避免。本节最后将讨论过度设计的影响,以及如何在设计阶段使用一些良好的实践来减轻这些影响。第二部分介绍了这种高性能设计的soc级和系统级验证所涉及的挑战,其中混合信号IP的百分比增加。它讨论了一些特定的ip以及如何处理模拟和数字域之间的复杂交互。然后涵盖了速度和准确性之间的权衡以及相关的最佳实践;并涵盖了其他一些常见的挑战,如港口顺序不匹配等。最后一节讨论了测试高性能设计的挑战,特别是考虑到过程和设计可变性。长期以来,半导体的成品率一直受到基于随机粒子的问题的限制,因此测试面向检测此类缺陷。然而,在65nm及以下的特征尺寸上,随着向挤压性能和功率的转变,系统和工艺的可变性问题已经开始对成品率的影响产生重大影响。为了跟上这一点,测试必须适应能够在存在可变性的情况下识别好设备和坏设备或不太好的设备。本节在快速总结基础知识后,将讨论高级主题,如功率感知,时间感知和可变性感知测试技术以及片上测试结构和技术,可用于预测设计的速度和功率之间的相关性。建议的教程快速触及学生,新工程师和管理人员感兴趣的基础知识,但主要侧重于涵盖当今行业在低功耗空间中复杂高性能soc的设计,验证和测试阶段所面临的关键挑战。由于它涵盖了多个领域,内容应该是广泛的学生,学者和工程师感兴趣的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Tutorial T5: High Performance Low Power Designs - Challenges and Best practices in Design, Verification and Test
Demand for highly mobile and lower form-factor designs is driving semiconductor industry towards lower and lower power envelopes even for complex SOCs. With performance targets being expected to grow with every advancement in process technology, it becomes very difficult to achieve low power targets especially with shrinking geometries resulting in more pronounced second order effects in devices and interconnect. This tutorial is intended to cover some key challenges and best practices of design, verification and test domains for high performance ICs in low power space. First section starts off by explaining the basic trade-off between performance and power followed by how margins are used in various phases of design and analysis for better predictability of silicon behavior. It then covers the need for custom designs which could impact time-to-market but cannot be avoided due to the tighter and tighter specs on power and performance with every technology shift. This section concludes by discussing the impacts of overdesign and how they can be alleviated with some good practices during design phase. Second section covers the challenges involved in SOC-level and system-level verification of such high-performance designs with increased percentage of mixed-signal IP in them. It talks about some specific IPs and how to handle complex interactions between analog and digital domains there. It then covers the trade-off seen between speed and accuracy and associated best practices; and also covers some other common challenges like port order mismatches, etc. The final section addresses the challenge of testing the high performance designs especially given the process and design variability. For a long time semiconductor yield has been limited by random particle based issues and accordingly testing was geared towards detecting such defects. However, at feature sizes 65nm and below and with increased shift towards squeezing performance and power, systematic and process variability issues have begun to contribute significantly towards the yield fallout. In keeping up with this, testing has to adapt to be able to identify good devices from bad or not-so-good devices in the presence of variability. This section, after quickly summarizing the fundamentals will address advanced topics such as power-aware, timing-aware and variability aware test techniques and on-chip test structures and techniques that can be used to predict correlation between speed and power of the designs. The proposed tutorial quickly touches upon the basics to be of interest to students, new engineers and managers but primarily focuses on covering the key challenges seen across the industry today in design, verification and test phases of complex high performance SOCs in low power space. Since it covers multiple domains, the content should be of interest to a wide range of students, scholars and engineers.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信