{"title":"Any Capacitor Stable LVR Using Sub-unity Gain Positive Feedback Loop in 65nm CMOS","authors":"S. Singh, N. Bansal","doi":"10.1109/VLSID.2015.50","DOIUrl":null,"url":null,"abstract":"In this paper a fully on-chip, any capacitor stable linear voltage regulator (LVR) using sub-unity gain positive feedback loop and NMOS pass element is presented. Sub-unity gain of the loop decouples loop stability from output capacitance value thus realizing any capacitor stable regulator. Regulator is shown to be stable for wide range of output capacitance values from 1nF to 40μF. Regulator output settles i n 0.5μs with peak to peak voltage variation of 158mV for a load current step of 0 to 115mA in 0.14μs with 1nF output capacitance. Response becomes better for higher values of output capacitance. LVR generates 1.25V output from 1.6V input while using another 3.0V input supply and occupies 0.18mm2 in 65nm CMOS.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"51 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 28th International Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSID.2015.50","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
In this paper a fully on-chip, any capacitor stable linear voltage regulator (LVR) using sub-unity gain positive feedback loop and NMOS pass element is presented. Sub-unity gain of the loop decouples loop stability from output capacitance value thus realizing any capacitor stable regulator. Regulator is shown to be stable for wide range of output capacitance values from 1nF to 40μF. Regulator output settles i n 0.5μs with peak to peak voltage variation of 158mV for a load current step of 0 to 115mA in 0.14μs with 1nF output capacitance. Response becomes better for higher values of output capacitance. LVR generates 1.25V output from 1.6V input while using another 3.0V input supply and occupies 0.18mm2 in 65nm CMOS.