Statistical Analysis of 64Mb SRAM for Optimizing Yield and Write Performance

Abstract

SRAMs occupy more than 50% of die area in high performance SoCs. Device variations in advanced technology nodes limit SRAM cell performance and yield. Maximum write time defines performance limited yield for SRAMs. In this work, we estimate sensitivity of write time of a 6T SRAM cell to variations in different devices through Design of Experiments (DoE) method. We evaluate multiple write-time models and estimate variation in yield for given write time specification. This work enables a performance vs yield trade-off and formalizes a Design for Yield (DFY) analysis. We benchmark multiple yield models and show that nonlinear models for write time are more accurate. We also estimate minimum required write time for different yield targets. We find that to achieve a target yield of 99%, SRAM designer needs to budget a write time of 656 ps when designing a 64Mb SRAM in 65nm technology. For a target yield of 90% with 1Mb capacity, 573 ps write time is sufficient and is 12% faster.