{"title":"Thermal-Aware Test Data Compression Using Dictionary Based Coding","authors":"R. Karmakar, S. Chattopadhyay","doi":"10.1109/VLSID.2015.14","DOIUrl":null,"url":null,"abstract":"In this paper, we have proposed a new thermal-aware test data compression technique using dictionary based coding. Huge test data volume and chip temperature are two major challenges for test engineers. Temperature of a chip can be reduced to a large extent by minimizing transition count in scan chains using efficient don't-care filling. On the other hand, high compression ratio can be achieved by filling the don't-cares intelligently to get more similar sub-vectors from test vectors. Although, both of the problems rely on don't-care bit filling, most of the existing works have considered them as separate problems. In our work, we have combined both temperature reduction and compression into a single problem and solved it. We present an intermediate approach that performs a trade-off between temperature and compression ratio. Experimental results on ISCAS'89 and ITC'99 benchmarks show the flexibility of the proposed method to achieve a balance between temperature and compression ratio.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"76 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 28th International Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSID.2015.14","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
In this paper, we have proposed a new thermal-aware test data compression technique using dictionary based coding. Huge test data volume and chip temperature are two major challenges for test engineers. Temperature of a chip can be reduced to a large extent by minimizing transition count in scan chains using efficient don't-care filling. On the other hand, high compression ratio can be achieved by filling the don't-cares intelligently to get more similar sub-vectors from test vectors. Although, both of the problems rely on don't-care bit filling, most of the existing works have considered them as separate problems. In our work, we have combined both temperature reduction and compression into a single problem and solved it. We present an intermediate approach that performs a trade-off between temperature and compression ratio. Experimental results on ISCAS'89 and ITC'99 benchmarks show the flexibility of the proposed method to achieve a balance between temperature and compression ratio.