Block-Level Electro-Migration Analysis (BEMA) for Safer Product Life

Abstract

With technologies like Fully Depleted Silicon On Insulator (FDSOI), the high performance transistor devices push very good Ion but the metallization is not equipped to handle it reliably for different Power-on-Hours(POH) needs. Current density is not scaling down proportionally with downscaling and hence resulting into more stress on interconnects for these advanced nodes. Traditional method of running electromigration(EM) checks at the final stage of the Intellectual Property (IP) development cycle - after integration of all building blocks at the top level - becomes a complex and time consuming activity. This method has two basic challenges - 1) Not scalable for large memory instances 2) Will take at least 2 man weeks per compiler. In this paper we present a new methodology of checking electromigration at the block level. This methodology is not restricted to Memories and can be applied to any Custom IP that is hierarchical and is developed top-down. This greatly reduces the effort needed to clean up electromigration and joule heating violations at the top level. The correlation between the full cut and block level results is within 2%. Running this analysis at block-level reduces any limit on the design size. Cumulative runtimes at block level turns out to be much smaller than a single run at the top level. This methodology saves us ~8X on the run time and ~14X on the total memory utilization. These gains are in addition to the fact that the product cycle time is reduced because we are able to run the analysis at an earlier stage where the corrections are practically possible.