2015 28th International Conference on VLSI Design最新文献_第7页

CERI: Cost-Effective Routing Implementation Technique for Network-on-Chip 片上网络的低成本路由实现技术

2015 28th International Conference on VLSI Design Pub Date : 2015-02-05 DOI: 10.1109/VLSID.2015.15

Rimpy Bishnoi, V. Laxmi, M. Gaur, R. H. Ramlee, Mark Zwolinski

{"title":"CERI: Cost-Effective Routing Implementation Technique for Network-on-Chip","authors":"Rimpy Bishnoi, V. Laxmi, M. Gaur, R. H. Ramlee, Mark Zwolinski","doi":"10.1109/VLSID.2015.15","DOIUrl":"https://doi.org/10.1109/VLSID.2015.15","url":null,"abstract":"To deal with the communication challenges of current and future many-core architectures, Network-on-Chip (NoC) has been proposed as a promising alternative. Regular 2D mesh topology is the most preferred design choice for NoCs. Hardware failures owing to manufacturing, wearout, aging etc., however, may disrupt the regularity of 2D mesh. Sustaining routing under these circumstances becomes a challenge. Though traditional table based routing method is flexible enough to handle any irregularity, it is neither scalable nor cost-effective solution. Scalable distributed logic based solutions like uLBDR have limited flexibility and work only in restricted architectural space despite complex switch design. To overcome these limitations, this paper presents CERI (CostEffective Routing Implementation), an efficient logic based routing capable of handling failure-induced irregularities in 2D mesh. Implementation of proposed approach does not require tables or a complex switch design. Performance analysis of CERI demonstrates its cost effectiveness as area and power requirements are reduced respectively by (14%) and (16%) than previously proposed logic based solution uLBDR.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129268465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Evaluating a Hardware-Based Approach for Detecting Resistive-Open Defects in SRAMs 评估一种基于硬件的sram阻性开放缺陷检测方法

2015 28th International Conference on VLSI Design Pub Date : 2015-02-05 DOI: 10.1109/VLSID.2015.74

F. Lavratti, L. Bolzani, F. Vargas, A. Calimera, E. Macii

引用次数: 1

Tutorial T6: FinFET Device Circuit Co-design: Issues and Challenges 课程T6: FinFET器件电路协同设计:问题与挑战

2015 28th International Conference on VLSI Design Pub Date : 2015-02-05 DOI: 10.1109/VLSID.2015.114

S. Dasgupta, B. Anand

{"title":"Tutorial T6: FinFET Device Circuit Co-design: Issues and Challenges","authors":"S. Dasgupta, B. Anand","doi":"10.1109/VLSID.2015.114","DOIUrl":"https://doi.org/10.1109/VLSID.2015.114","url":null,"abstract":"The race to the next process node of FinFETs becomes more prominent after the Intel's & TSMC's announcement to use tri-gate technology (FinFETs) commercially in below 20nm node. Last year, the revealed the 16nm FinFET process that by many measures is one of the most advanced semiconductor technologies. Most of the other semiconductor industries/foundries are expected to adopt FinFETs at 16/14 nm in order to keep pace imposed by the Intel and TSMC. However, similar to the problems faced by any new technology, FinFETs with sub-20 nm feature size also faces several design challenges. Most of these challenges arise due to technological restriction that again degrades its performances. Although, some performance boosters such as high permittivity spacers, enhances the device characteristics but has limited applicability in high-performance circuit applications. Researchers also explored various physical configurations/architectures to alleviate device-circuit co-design to improve the overall performance. However, contradictory observations have been made with respect to device and circuit immunity to random variations that result in an ambiguity about their true applicability. Therefore, it is necessary to thoroughly investigate these novel device architectures with their circuit suitability and tolerance to random variations. Therefore, this tutorial explores the possibilities of dual-spacer (symmetric and asymmetric) architecture for the purpose and its impact of high performance logic circuit/SRAM applications with its tolerance limits to random variations.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132601432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Power Optimization Techniques for DDR3 SDRAM DDR3 SDRAM的功耗优化技术

2015 28th International Conference on VLSI Design Pub Date : 2015-02-05 DOI: 10.1109/VLSID.2015.59

P. Panda, Vishal Patel, Praxal Shah, Namita Sharma, V. Srinivasan, D. Sarma

引用次数: 0

RELSPEC: A Framework for Early Reliability Refinement of Embedded Applications RELSPEC:嵌入式应用早期可靠性改进框架

2015 28th International Conference on VLSI Design Pub Date : 2015-02-05 DOI: 10.1109/VLSID.2015.12

S. Ghosh, Aritra Hazra, Soumyajit Dey

引用次数: 3

Hardware Solution for Real-Time Face Recognition 实时人脸识别的硬件解决方案

2015 28th International Conference on VLSI Design Pub Date : 2015-02-05 DOI: 10.1109/VLSID.2015.19

Gopinath Mahale, H. Mahale, Arnav Goel, S. Nandy, S. Bhattacharya, R. Narayan

{"title":"Hardware Solution for Real-Time Face Recognition","authors":"Gopinath Mahale, H. Mahale, Arnav Goel, S. Nandy, S. Bhattacharya, R. Narayan","doi":"10.1109/VLSID.2015.19","DOIUrl":"https://doi.org/10.1109/VLSID.2015.19","url":null,"abstract":"The objective of this paper is to come up with a scalable modular hardware solution for real-time Face Recognition (FR) on large databases. Existing hardware solutions use algorithms with low recognition accuracy suitable for real-time response. In addition, database size for these solutions is limited by on-chip resources making them unsuitable for practical real-time applications. Due to high computational complexity we do not choose algorithms in literature with superior recognition accuracy. Instead, we come up with a combination of Weighted Modular Principle Component Analysis (WMPCA) and Radial Basis Function Neural Network (RBFNN) which outperforms algorithms used in existing hardware solutions on highly illumination and pose variant face databases. We propose a hardware solution for real-time FR which uses parallel streams to perform independent modular computations. A salient feature of proposed hardware solution is that we store a major part of data on off-chip memory in a novel format, so that latencies experienced accessing off-chip memory does not impact performance. This enables us to work on databases of very large sizes. To test functional correctness, the proposed architecture is synthesized and tested on Virtex-6 LX550T FPGA. This emulated system is able to perform 450 recognitions per second on images of size 128 × 128 with 450 classes.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125217174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Diagnostic Tests for Pre-bond TSV Defects 粘结前TSV缺陷的诊断测试

2015 28th International Conference on VLSI Design Pub Date : 2015-02-05 DOI: 10.1109/VLSID.2015.71

Bei Zhang, V. Agrawal

引用次数: 12

Efficient Peak Power Estimation Using Probabilistic Cost-Benefit Analysis 基于概率成本效益分析的高效峰值功率估计

2015 28th International Conference on VLSI Design Pub Date : 2015-02-05 DOI: 10.1109/VLSID.2015.68

Hadi Hajimiri, Kamran Rahmani, P. Mishra

引用次数: 8

Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming 基于动态规划的紧凑型可逆进位前瞻加法器设计

2015 28th International Conference on VLSI Design Pub Date : 2015-02-05 DOI: 10.1109/VLSID.2015.46

N. J. Lisa, H. Babu

引用次数: 8

A Flexible Scalable Hardware Architecture for Radial Basis Function Neural Networks 径向基函数神经网络的灵活可扩展硬件结构

2015 28th International Conference on VLSI Design Pub Date : 2015-02-05 DOI: 10.1109/VLSID.2015.91

M. Mohammadi, N. Satpute, Rohit Ronge, J. Chandiramani, S. Nandy, Aamir Raihan, Tanmay Verma, R. Narayan, S. Bhattacharya

{"title":"A Flexible Scalable Hardware Architecture for Radial Basis Function Neural Networks","authors":"M. Mohammadi, N. Satpute, Rohit Ronge, J. Chandiramani, S. Nandy, Aamir Raihan, Tanmay Verma, R. Narayan, S. Bhattacharya","doi":"10.1109/VLSID.2015.91","DOIUrl":"https://doi.org/10.1109/VLSID.2015.91","url":null,"abstract":"Radial Basis Function Neural Networks (RBFNN) are used in variety of applications such as pattern recognition, control and time series prediction and nonlinear identification. RBFNN with Gaussian Function as the basis function is considered for classification purpose. Training is done offline using K-means clustering method for center learning and Pseudo inverse for weight adjustments. Offline training is done since the objective function with any fixed set of weights can be computed and we can see whether we make any progress in training. Moreover, minimum of the objective function can be computed to any desired precision, while with online training none of these can be done and it is more difficult and unreliable. In this paper we provide the comparison of RBFNN implementation on FPGAs using soft core processor based multi-processor system versus a network of Hyper Cells [8], [13]. Next we propose three different partitioning structures (Linear, Tree and Hybrid) for the implementation of RBFNN of large dimensions. Our results show that implementation of RBFNN on a network of Hyper Cells using Hybrid Structure, has on average 26x clock cycle reduction and 105X improvement in the performance over that of multi-processor system on FPGAs.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127852343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3