Tutorial T6: FinFET Device Circuit Co-design: Issues and Challenges

The race to the next process node of FinFETs becomes more prominent after the Intel's & TSMC's announcement to use tri-gate technology (FinFETs) commercially in below 20nm node. Last year, the revealed the 16nm FinFET process that by many measures is one of the most advanced semiconductor technologies. Most of the other semiconductor industries/foundries are expected to adopt FinFETs at 16/14 nm in order to keep pace imposed by the Intel and TSMC. However, similar to the problems faced by any new technology, FinFETs with sub-20 nm feature size also faces several design challenges. Most of these challenges arise due to technological restriction that again degrades its performances. Although, some performance boosters such as high permittivity spacers, enhances the device characteristics but has limited applicability in high-performance circuit applications. Researchers also explored various physical configurations/architectures to alleviate device-circuit co-design to improve the overall performance. However, contradictory observations have been made with respect to device and circuit immunity to random variations that result in an ambiguity about their true applicability. Therefore, it is necessary to thoroughly investigate these novel device architectures with their circuit suitability and tolerance to random variations. Therefore, this tutorial explores the possibilities of dual-spacer (symmetric and asymmetric) architecture for the purpose and its impact of high performance logic circuit/SRAM applications with its tolerance limits to random variations.