Low-Area and Low-Power Reconfigurable Architecture for Convolution-Based 1-D DWT Using 9/7 and 5/3 Filters

This paper presents an optimized adder-based formulation for low-area and low-power implementation of 1-D DWT using 5/3 and 9/7 filters. Not only the number of adders is minimized, the number bit-shifts also minimized in the formulation to reduce the bit-width of intermediate results. Separate Adder-based designs are derived using the proposed formulation for 9/7 filter, 5/3 filter and a reconfigurable structure for both 9/7 and 5/3 filters. The proposed structure for 9/7 filter requires 19 adders and 11 hardwired-shifters (shifters are implemented by rewiring only) and computes two DWT components in every clock cycle. It requires only 8 registers for two-stage pipeline implementation. The proposed reconfigurable structure involves a small overhead of complexity in terms of one adder, 2 MUXes, 2 registers, and 4 extra hardwired-shifters than the proposed 9/7 structure to have the reconfigurable design. The proposed reconfigurable structure supports higher usable frequency (without pipelining), and provides double the throughput per clock cycle compared to that of best available similar structure with marginally higher area complexity. ASIC synthesis results show that the proposed pipelined structure for 9/7 filters involves nearly 70% less ADP and 82% less EPO than the best of DA-based structures. Further, it involves less than half the ADP and 47% less EPO than the corresponding recent multiplier-based structure. The proposed reconfigurable structure involves less than one-third the EPO and ADP of similar existing structure. The proposed design indicates the superiority of adder-based design over DA-based design as well as conventional multiplier-based design.