{"title":"Ultra-fast Cap-less LDO for Dual Lane USB in 28FDSOI","authors":"S. Singh, Gautam Dey Kanungo","doi":"10.1109/VLSID.2015.49","DOIUrl":null,"url":null,"abstract":"A fully on-chip LDO for very fast load transient up to 15mA/nsec in 28nm FDSOI is presented. Proposed LDO capitalizes on technological boost given to on-chip capacitance density and MOS current drives to implement conventional compensation technique without using off-chip capacitor. Dominant output pole enables the LDO to achieve its superior load transient performance. Proposed LDO generates 1.0V output from a 1.6V input supply and has maximum output current capacity of 15mA. Simulated worst case PSR at 10kHz is-23dB and current efficiency is 93% at maximum load condition. Three such LDOs are combined to provide dedicated 1.0V supplies to dual lane USB cores and their PLL. Area including reference generator, three LDO and all on-chip capacitances is 0.2mm2.","PeriodicalId":123635,"journal":{"name":"2015 28th International Conference on VLSI Design","volume":"598 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-02-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 28th International Conference on VLSI Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSID.2015.49","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
A fully on-chip LDO for very fast load transient up to 15mA/nsec in 28nm FDSOI is presented. Proposed LDO capitalizes on technological boost given to on-chip capacitance density and MOS current drives to implement conventional compensation technique without using off-chip capacitor. Dominant output pole enables the LDO to achieve its superior load transient performance. Proposed LDO generates 1.0V output from a 1.6V input supply and has maximum output current capacity of 15mA. Simulated worst case PSR at 10kHz is-23dB and current efficiency is 93% at maximum load condition. Three such LDOs are combined to provide dedicated 1.0V supplies to dual lane USB cores and their PLL. Area including reference generator, three LDO and all on-chip capacitances is 0.2mm2.