2021 25th International Symposium on VLSI Design and Test (VDAT)最新文献

Radiation Hardened Area-Efficient 10T SRAM Cell for Space Applications 用于空间应用的抗辐射面积高效10T SRAM单元

2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9601130

Sayeed Ahmad, N. Alam, M. Hasan

引用次数: 2

Area-Time Scalable High Radix Montgomery Modular Multiplier for Large Modulus 大模的区域-时间可伸缩高基数Montgomery模乘法器

2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9601001

Venkata Reddy Kolagatla, Vivian Desalphine, D. Selvakumar

{"title":"Area-Time Scalable High Radix Montgomery Modular Multiplier for Large Modulus","authors":"Venkata Reddy Kolagatla, Vivian Desalphine, D. Selvakumar","doi":"10.1109/VDAT53777.2021.9601001","DOIUrl":"https://doi.org/10.1109/VDAT53777.2021.9601001","url":null,"abstract":"Adoption of large modulus and field sizes for RSA and ECC are of the norm for meeting present day’s security requirements and goals. Modular multiplication (MM) is the key computational unit for both and requires large hardware resources (area) and incurs huge latency. Typically, Montgomery Modular Multiplier and Interleaved Modular Multiplier are being adopted for RSA and ECC respectively for designing efficient hardware. Lower Area-time (AT) product is the key design metric to consider both latency (time to compute one MM) and area together as a combined metric. Combinational circuit to compute partial products of a particular modulus for higher radices increases area and critical path, reduces frequency, and latency. Here, the increase in area dominates the reduction in latency with respect to radix, resulting in an increased AT metric for the given modulus. This work presents a table look up technique for the multiplication factors which is used to compute partial products of modulus in MR-MMM (Multi-Radix Montgomery Modular Multiplier). This approach reduces the AT metrics with increasing radices for a given larger modulus enabling an AT scalable hardware and has been proven on Virtex 7 and 6 FPGAs for modulus 256 to 4096 with radices 2 to 212.","PeriodicalId":122393,"journal":{"name":"2021 25th International Symposium on VLSI Design and Test (VDAT)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121209625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Behaviour of FinFET Inverter’s Effective Capacitances in Low-Voltage Domain 低电压域FinFET逆变器有效电容的行为

2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9601052

Sarita Yadav, Nitanshu Chauhan, A. Pandey, R. Pratap, B. Anand

引用次数: 0

Analytical Modelling of a CMOS Inter Spike Interval Decoder for Resistive Crossbar based Brain Inspired Computing 基于脑启发计算的电阻交叉棒CMOS尖峰间隔解码器的解析建模

2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9600953

Sahibia Kaur Vohra, Sherin A. Thomas, Mahendra Sakare, D. Das

引用次数: 1

Analysis of Standard Cells performance for In0.53Ga0.47As FinFET with underlap fin length for High Speed Applications 高速下叠翅In0.53Ga0.47As FinFET标准电池性能分析

2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9600972

Jay Pathak, A. Darji

引用次数: 0

Automated Design of Analog Circuits using Machine Learning Techniques 使用机器学习技术的模拟电路自动设计

2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9601131

S. Devi, Gourav Tilwankar, R. Zele

引用次数: 5

Formal Verification and Analysis of a Pseudo Random Number Generator 伪随机数生成器的形式化验证与分析

2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9601109

D. Selvakumar, J. Mervin, Shashikala Pattanshetty, Vivian Desalphine

引用次数: 0

LightFPGA: Scalable and Automated FPGA Acceleration of LightGBM for Machine Learning Applications LightFPGA:用于机器学习应用的可扩展和自动FPGA加速

2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9600900

Alish Kanani, Swar Vaidya, H. Agarwal

引用次数: 0

An All-CMOS Supply, Temperature and Process Invariant Hybrid Current Reference For Power Efficient IoT Applications 一种全cmos电源，温度和工艺不变混合电流基准，用于高能效物联网应用

2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9601082

Soumya Tapse, S. Jandhyala, Adithya Reddy Banti

引用次数: 0

A Hardware-Software Co-design based Approach for Development of a Distributed DAQ System using FPGA 基于FPGA的分布式数据采集系统的软硬件协同设计方法

2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9600989

A. Krishnan, M. H. Supriya, N. Sivanandan

{"title":"A Hardware-Software Co-design based Approach for Development of a Distributed DAQ System using FPGA","authors":"A. Krishnan, M. H. Supriya, N. Sivanandan","doi":"10.1109/VDAT53777.2021.9600989","DOIUrl":"https://doi.org/10.1109/VDAT53777.2021.9600989","url":null,"abstract":"Data acquisition systems are required to condition the low-level analog signals from various sensors and to convert them into digital format in order to facilitate downstream processing. Distributed DAQ systems are commonly used in SONAR systems, as a large number of acoustic sensors are used in big platforms and the sensors are physically distributed. The data collected by the distributed DAQ systems are transmitted to a central processing system in real-time where further processing of the data is done. The operating environment of the underwater system can impose severe restrictions on the design of the DAQ system. This paper presents a hardware-software co-design based approach to implementing a resource-efficient FPGA-based distributed DAQ system. Here, the functionality of deterministic data transmission through Ethernet is implemented using RTL modules, and remote health monitoring and configuration control functionalities with TCP/IP stack support are implemented in a soft-processor inside FPGA. To reduce the number of external cables and the FPGA resource utilization, a single Ethernet MAC is shared between processor and RTL modules using AXI switches. Synchronized sampling of sensors is an important requirement in distributed DAQ systems. In this paper, synchronization is achieved by implementing the IEEE1588 precision time protocol in FPGA. By implementing the timestamping of the PTP messages at the RGMII interface, synchronization accuracy close to 300ns was achieved. The implementation was done on Artix7 FPGA from Xilinx with a resource utilization of 36K LUTs and 43K flip-flops. MicroBlaze soft-processor was used with 100 MHz clock and the Synchronization Timer was generated using a 200 MHz clock.","PeriodicalId":122393,"journal":{"name":"2021 25th International Symposium on VLSI Design and Test (VDAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124194730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0