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2021 25th International Symposium on VLSI Design and Test (VDAT)最新文献

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Tutorials in VDAT 2021 [4 abstracts] VDAT 2021教程[4个摘要]
2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9600948
{"title":"Tutorials in VDAT 2021 [4 abstracts]","authors":"","doi":"10.1109/VDAT53777.2021.9600948","DOIUrl":"https://doi.org/10.1109/VDAT53777.2021.9600948","url":null,"abstract":"Provides an abstract for each of the tutorial presentations and may include a brief professional biography of each presenter. The complete presentations were not made available for publication as part of the conference proceedings.","PeriodicalId":122393,"journal":{"name":"2021 25th International Symposium on VLSI Design and Test (VDAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125818641","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On Disabling Prefetcher to Amplify Cache Side Channels 禁用预取器以放大缓存侧通道
2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9600982
N. Boran, Kenrick Pinto, B. Menezes
{"title":"On Disabling Prefetcher to Amplify Cache Side Channels","authors":"N. Boran, Kenrick Pinto, B. Menezes","doi":"10.1109/VDAT53777.2021.9600982","DOIUrl":"https://doi.org/10.1109/VDAT53777.2021.9600982","url":null,"abstract":"Side-channel attacks exploit the hardware implementation of processors to extract sensitive data. Attacks that target shared resources between the victim and the attacker are prominent. A shared cache (available in today’s multi-core systems) between the attacker and victim has been shown to create a covert channel capable of leaking the private key. An attacker can extract the key by tracking the victim’s memory access pattern through the shared cache. Prefetchers introduce noise in the attack by speculatively bringing data into the cache that the victim may not use. This paper presents a denial of service (DoS) attack on the prefetcher to prevent it from generating memory accesses that interfere with the side-channel attack. The proposed attack aims to significantly reduce the number of prefetches generated to enable faster key retrieval. Our results show that the private key can be extracted with only 21% additional time in the presence of a prefetcher when the proposed attack is run (compared to a system with no prefetcher).","PeriodicalId":122393,"journal":{"name":"2021 25th International Symposium on VLSI Design and Test (VDAT)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126752941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Dual Stage Encoding Technique to Minimize Cross Coupling across NoC Links 最小化NoC链路交叉耦合的双级编码技术
2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9601003
S. Dev, S. Krishna, S. Archana, Rose George Kunthara, K. Neethu, Rekha K. James
{"title":"Dual Stage Encoding Technique to Minimize Cross Coupling across NoC Links","authors":"S. Dev, S. Krishna, S. Archana, Rose George Kunthara, K. Neethu, Rekha K. James","doi":"10.1109/VDAT53777.2021.9601003","DOIUrl":"https://doi.org/10.1109/VDAT53777.2021.9601003","url":null,"abstract":"Network-on-Chip (NoC) has been a viable solution for resolving the complexities associated with inter-processor communications in a Chip Multi Processor (CMP). NoC accounts for a significant portion of the total power consumed by a CMP. In a standard NoC system, only a fraction of power dissipation occurs due to static/leakage, while the rest is due to dynamic power. Dynamic dissipation includes self-switching and coupling switching dissipations, with the latter accounting for a significant part of total power dissipated. Several coding methods exist to minimize this dynamic power dissipation in NoC links. In this paper, we propose Algorithm 1 to reduce self-switching transitions and Algorithm 2 & 3 to lower coupling switching transitions in between the serial links, with Encoder/decoder modules placed at Network-Interface(NI) level. Simulations done on Xilinx Vivado design suite showed a maximum reduction of 64% in coupling switching activity compared to existing schemes.","PeriodicalId":122393,"journal":{"name":"2021 25th International Symposium on VLSI Design and Test (VDAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130315847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Organizing Committees for VDAT-2021 VDAT-2021组委会
2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/vdat53777.2021.9600992
{"title":"Organizing Committees for VDAT-2021","authors":"","doi":"10.1109/vdat53777.2021.9600992","DOIUrl":"https://doi.org/10.1109/vdat53777.2021.9600992","url":null,"abstract":"","PeriodicalId":122393,"journal":{"name":"2021 25th International Symposium on VLSI Design and Test (VDAT)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130691391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance Comparison of Single Level STT and SOT MRAM Cells for Cache Applications 用于高速缓存应用的单级STT和SOT MRAM单元性能比较
2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9601129
Ashish Sura, V. Nehra
{"title":"Performance Comparison of Single Level STT and SOT MRAM Cells for Cache Applications","authors":"Ashish Sura, V. Nehra","doi":"10.1109/VDAT53777.2021.9601129","DOIUrl":"https://doi.org/10.1109/VDAT53777.2021.9601129","url":null,"abstract":"The research on intrinsic spin of electrons results a new type of memory device, Spin-transfer-torque magnetic random access memory (STT-MRAM). The property of non-volatility, high endurance, and highly scalable feature size makes STT-MRAM a strong contender for futuristic memory technologies. The basic storage unit is magnetic tunnel junction (MTJ) device and data is read/write by tunnel magneto resistance (TMR) effect and STT mechanism. The high switching current and read disturb of STT-MRAM has forced researchers to shift to a newer technology spin-orbit-torque (SOT)-MRAM. The spin Hall effect (SHE) based SOT-MRAM provides non-volatility with negligible leakage, high performance and endurance with lower switching current. In this paper, we provide a performance comparison of STT-MRAM and SOT-MRAM cell. Further, array level comparison is performed using NVSIM platform. The simulation results show that the SOT MRAM possess lower write current and energy-efficient as compared to STT MRAM.","PeriodicalId":122393,"journal":{"name":"2021 25th International Symposium on VLSI Design and Test (VDAT)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131885009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Multi-Octave Frequency Range SerDes with a DLL Free Receiver 一个多倍频程范围SerDes与DLL免费接收器
2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9600917
R. Thukral, Mohit Goswami, Sharayu Jagtap, Sandeep Goyal, Shalabh Gupta
{"title":"A Multi-Octave Frequency Range SerDes with a DLL Free Receiver","authors":"R. Thukral, Mohit Goswami, Sharayu Jagtap, Sandeep Goyal, Shalabh Gupta","doi":"10.1109/VDAT53777.2021.9600917","DOIUrl":"https://doi.org/10.1109/VDAT53777.2021.9600917","url":null,"abstract":"A deserializer in a high-speed serial link typically uses a delay-locked loop (DLL) or a phase-locked loop (PLL) for phase alignment and sampling of the data signal. However, such DLLs or PLLs have a limited operating frequency range. In this architecture, we have proposed a DLL-free deserializer that can operate over a multi-octave frequency range, which is compatible with the TIA/EIA-644 LVDS standard. The serializer in the SerDes receives 21 bits of parallel data (from the digital system) at a bit rate up to 80 Mbps, serializes it to (up to) 560 Mbps into three channels, along with a 1/7th rate clock signal. The deserializer uses these signals for recovering the original bit-stream. The chip has been designed in SCL 180nm CMOS technology, using high-voltage devices, for backward compatibility with the system using 3.3V supply. The worst case power consumption (obtained from post layout simulations) is 173.25mW and 207.6mW for the serializer and the deserializer designs, respectively, which indicates a very significant improvement with respect to the available products.","PeriodicalId":122393,"journal":{"name":"2021 25th International Symposium on VLSI Design and Test (VDAT)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116245075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Process Development for Very Deep Etching of Silicon Using Two Layer Masks for Fabrication of Mechanically Decoupled MEMS Gyroscope 采用双层掩模深度刻蚀硅制备机械解耦MEMS陀螺仪的工艺开发
2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9600921
Deepak Kumar Sharma, J. John, G. Supriya, Ashwini Jambhalikar, M. S. Giridhar
{"title":"Process Development for Very Deep Etching of Silicon Using Two Layer Masks for Fabrication of Mechanically Decoupled MEMS Gyroscope","authors":"Deepak Kumar Sharma, J. John, G. Supriya, Ashwini Jambhalikar, M. S. Giridhar","doi":"10.1109/VDAT53777.2021.9600921","DOIUrl":"https://doi.org/10.1109/VDAT53777.2021.9600921","url":null,"abstract":"This work discusses the key issues associated with the process development for 200 μm thick structure for mechanically decoupled Silicon on Glass (SOG) MEMS gyroscope. The gyroscope discussed here is a single axis, in-plane moving device with capacitive driving, differential capacitive sensing and has an area of 2.6 × 2.4 cm2. Challenges involved in defining masks for High Aspect Ratio (HAR) etching of silicon using Bosch process to a depth of 200 μm through an opening of 8 μm are discussed. The HAR etching of silicon is achieved by using a novel approach of having dual layer masks of Aluminum and photoresist.","PeriodicalId":122393,"journal":{"name":"2021 25th International Symposium on VLSI Design and Test (VDAT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130469214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Randomized Montgomery Powering Ladder Exponentiation for Side-Channel Attack Resilient RSA and Leakage Assessment 一种随机Montgomery功率梯指数法用于侧信道攻击弹性RSA和泄漏评估
2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9601132
Venkata Reddy Kolagatla, J. Mervin, Shabbir Darbar, D. Selvakumar, Sankha Saha
{"title":"A Randomized Montgomery Powering Ladder Exponentiation for Side-Channel Attack Resilient RSA and Leakage Assessment","authors":"Venkata Reddy Kolagatla, J. Mervin, Shabbir Darbar, D. Selvakumar, Sankha Saha","doi":"10.1109/VDAT53777.2021.9601132","DOIUrl":"https://doi.org/10.1109/VDAT53777.2021.9601132","url":null,"abstract":"This paper presents a randomized Montgomery Powering Ladder Modular Exponentiation (RMPLME) scheme for side channel attacks (SCA) resistant Rivest-Shamir-Adleman (RSA) and its leakage resilience analysis. This method randomizes the computation time of square-and-multiply operations for each exponent bit of the Montgomery Powering Ladder (MPL) based RSA exponentiation using various radices (Radix – 2, 22, and 24) based Montgomery Modular multipliers (MMM) randomly. The randomized computations of RMPLME generates non-uniform timing channels information and power traces thus protecting against SCA. In this work, we have developed and implemented a) an unmasked right-to-left Montgomery Modular Exponentiation (R-L MME), b) MPL exponentiation and c) the proposed RMPLME schemes for RSA decryption. All the three realizations have been assessed for side channel leakage using Welch’s t-test and analyzed for secured realizations based on degree of side channel information leakage. RMPLME scheme shows the least side-channel leakage and resilient against SPA, DPA, C-Safe Error, CPA and Timing Attacks.","PeriodicalId":122393,"journal":{"name":"2021 25th International Symposium on VLSI Design and Test (VDAT)","volume":"1999 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131102375","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High Sensitivity and Power Efficient Heater Structure for Bulk Micromachined Thermal Accelerometer 大型微机械热加速度计的高灵敏度和高能效加热器结构
2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9601046
R. Mukherjee, Joydeep Basu, P. K. Guha
{"title":"High Sensitivity and Power Efficient Heater Structure for Bulk Micromachined Thermal Accelerometer","authors":"R. Mukherjee, Joydeep Basu, P. K. Guha","doi":"10.1109/VDAT53777.2021.9601046","DOIUrl":"https://doi.org/10.1109/VDAT53777.2021.9601046","url":null,"abstract":"In MEMS based thermal convective accelerometers, the structure of the constituent microheater plays a crucial role in determining the sensitivity of the accelerometer. This paper reports the sensitivity improvement of a dual axis thermal accelerometer using a cross shaped heater structure. In a conventional heater design, the peak heater temperature generated at the center of the cavity offers lower temperature gradient at the position of the temperature sensors situated afar. As a result, the sensitivity obtainable from the thermal accelerometer becomes low. The sensitivity can be improved by generating the peak temperature at the side arms which are used to suspend the heater structure. This has been accomplished in this work using a cross shaped heater where the peak temperature is generated at the cross arms of the heater. Hence, the temperature gradient is higher near the temperature sensors, leading to improved sensitivity of the accelerometer. The sensitivity achieved using such a cross shaped heater is 0.36 K/g at a peak heater temperature of 615 K and having power requirement of 29.6 mW. The proposed heater structure can also be employed in other microsystem devices like gyroscope and thermal flow sensor for improving their performance.","PeriodicalId":122393,"journal":{"name":"2021 25th International Symposium on VLSI Design and Test (VDAT)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117308972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Broadband CMOS RF Logarithmic Power Detector for sub-6 GHz 5G Applications 6ghz以下5G应用的宽带CMOS RF对数功率检测器
2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9601080
Saurabh Katre, Shubham Tirmanwar, D. Ghosh
{"title":"Broadband CMOS RF Logarithmic Power Detector for sub-6 GHz 5G Applications","authors":"Saurabh Katre, Shubham Tirmanwar, D. Ghosh","doi":"10.1109/VDAT53777.2021.9601080","DOIUrl":"https://doi.org/10.1109/VDAT53777.2021.9601080","url":null,"abstract":"This paper describes the design of an RF power detector which has broad bandwidth and high dynamic range. The proposed RF power detector includes a low noise amplifier (LNA), limiting amplifiers, a peak detector and an adder circuit. The amplifier circuits uses cascode structure and inductive shunt peaking to achieve wide operating frequency range with band pass matching network for matching the RF input to 50Ω. Designed using UMC 180nm RFCMOS, the power detector circuit provides a largely linear relation between input logarithmic power and output DC voltage for the frequency range from 300 MHz to 5.4 GHz. The percentage bandwidth is 178.94%. The RF power detector circuit is tested for input power ranging from −70dBm to 0 dBm. The circuit exhibits dynamic range of 50 dB from 300 MHz to 5.4GHz and 70 dB from 700MHz to 4 GHz. This makes RF power detector suitable for broadband use in the sub-6 GHz 5G applications.","PeriodicalId":122393,"journal":{"name":"2021 25th International Symposium on VLSI Design and Test (VDAT)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123465112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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