2021 25th International Symposium on VLSI Design and Test (VDAT)最新文献_第4页

Behavior of LDMOS transistors at cryogenic temperature - An experiment based analysis LDMOS晶体管在低温下的性能——基于实验的分析

2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9601012

Kaushal Kumari Neeraj, N. Mohapatra

引用次数: 1

High Speed and Power Efficient Multiplexer based Matrix Vector Multiplication for LSTM Network 基于高速节能复用器的LSTM网络矩阵向量乘法

2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9601075

Tresa Joseph, T. Bindiya

引用次数: 1

Modeling of Thermal Properties of Semiconducting Monolayer MoSe2 and WSe2 半导体单层MoSe2和WSe2的热性能建模

2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9600966

Yuvam Bhateja, Joshua Roy Palathinkal, Tamajeet Mandal, P. Roy, D. Saha

{"title":"Modeling of Thermal Properties of Semiconducting Monolayer MoSe2 and WSe2","authors":"Yuvam Bhateja, Joshua Roy Palathinkal, Tamajeet Mandal, P. Roy, D. Saha","doi":"10.1109/VDAT53777.2021.9600966","DOIUrl":"https://doi.org/10.1109/VDAT53777.2021.9600966","url":null,"abstract":"In this work, first-principles based calculations of thermal properties of monolayer group-6 transition metal dichalcogenides (TMDs) viz. MoSe2 and WSe2 are reported. Owing to the distinctive electronic, optical, and thermal properties, the TMDs have emerged as the suitable candidates for designing next-generation ultra-thin nanodevices. Thus, accurate estimation of heat dissipation across any two-dimensional (2D) atomically thin layer has become crucial. In order to determine thermal transport, we need to assess different intrinsic properties of the 2D materials. A large value of thermal conductivity will ensure better heat transmission across the channel of any high-performance device. Therefore, modeling of different parameters such as mode dependent group velocities, phonon mean free path, etc. has become extremely important.In this study, we adopt a multi-scale modeling approach for determining phonon group velocities of semiconducting MoSe2 and WSe2 crystals. Room temperature air stability of single layer MoSe2 and single layer WSe2 are comparable with that of the other group-6 TMDs. Moreover, the semiconducting 2H phases of both the crystals are dynamically stable. The results reported in this work will be useful for developing closed-form expression of specific heat and thermal conductivity of semiconducting TMDs which are the potential channel materials for sub-10 nm channel length transistors.","PeriodicalId":122393,"journal":{"name":"2021 25th International Symposium on VLSI Design and Test (VDAT)","volume":"231 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116200710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Hardware Acceleration of SpMV Multiplier for Deep Learning 用于深度学习的SpMV乘法器的硬件加速

2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9600988

Mahesh Mahadurkar, N. Sivanandan, S. Kala

{"title":"Hardware Acceleration of SpMV Multiplier for Deep Learning","authors":"Mahesh Mahadurkar, N. Sivanandan, S. Kala","doi":"10.1109/VDAT53777.2021.9600988","DOIUrl":"https://doi.org/10.1109/VDAT53777.2021.9600988","url":null,"abstract":"Deep Learning techniques are widely adopted in many computer vision tasks and are practically implemented in real-world systems. Deep learning is a promising method for machine learning, where complex functions can be learned directly from the data. Deep learning algorithms provide high accuracy for recognition tasks, while consuming significant resources for computation, compared to the conventional algorithms. State-of-the-art deep learning networks have hundreds of millions of parameters, which makes them less suitable for adoption in devices with constrained memory and power requirements like edge computing devices and mobile devices. Techniques like quantization and inducing sparsity, aims to reduce the total number of computations needed for deep learning inference. For portable embedded applications, general purpose computing hardware like GPPs (General Purpose Processors) and GPUs (Graphic Processing Units) are not preferred as these applications demand high energy efficiency. Field Programmable Gate Arrays (FPGAs) are suitable hardware solutions for edge computing, which gives better power consumption with increased flexibility. In this paper we propose a bandwidth-efficient sparse matrix-vector (SpMV) multiplier architecture for faster deep learning inference. Our architecture also reduces memory-bandwidth bottleneck present in hardware realization of deep learning algorithms. Proposed architecture can use the maximum available memory bandwidth of the computing device, using the multiple MAC (multiply and accumulate) channels. The proposed architecture has been implemented on Kintex-7 FPGA with an operating frequency of 270 MHz and gave significant performance gain when compared with existing implementation.","PeriodicalId":122393,"journal":{"name":"2021 25th International Symposium on VLSI Design and Test (VDAT)","volume":"209 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134000851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Quantum Circuit Design of RECTANGLE Lightweight Cipher 矩形轻量级密码的量子电路设计

2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9601011

P. Saravanan, J. Jenitha, S. R. Aasish, S. Sanjana

引用次数: 1

A 82μW Mixed-Mode sub-1V Bandgap reference with 25 ppm/°C Temperature Co-efficient with Simultaneous PTAT Generation 一个82μW的混合模式sub-1V带隙基准，温度系数为25 ppm/°C，可同时产生PTAT

2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-16 DOI: 10.1109/VDAT53777.2021.9600909

T. R. Varun, R. Nagulapalli, Immanuel Raja

引用次数: 12

Message from Program Chairs 节目主持人的信息

2021 25th International Symposium on VLSI Design and Test (VDAT) Pub Date : 2021-09-01 DOI: 10.1109/vdat53777.2021.9601119

引用次数: 0