High Speed and Power Efficient Multiplexer based Matrix Vector Multiplication for LSTM Network

Abstract

This paper proposes a multiplexer based technique for accelerating matrix vector multiplication (MVM) in long short term memory networks. The concept of multiple constant multiplication with separate generation and selection of partial products is used in this design. The most important benefit of the proposed architecture is the reduced implementation complexity in terms of cell area and power efficiency. A truncating method is effectively utilized with a guaranteed reduction in the hardware complexity and power consumption. For inner product computations, the input coefficients are truncated instead of being shifted, which in turn make use of combinational circuits replacing the sequential designs. Also, to improve the overall clock period, a novel design for inner product computations is envisaged, which uses modified multiplexer architecture instead of the existing method. The results show a reduction in the implementation complexity of the MVM with a significant power reduction of 14%.