A Multi-Octave Frequency Range SerDes with a DLL Free Receiver

R. Thukral, Mohit Goswami, Sharayu Jagtap, Sandeep Goyal, Shalabh Gupta
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Abstract

A deserializer in a high-speed serial link typically uses a delay-locked loop (DLL) or a phase-locked loop (PLL) for phase alignment and sampling of the data signal. However, such DLLs or PLLs have a limited operating frequency range. In this architecture, we have proposed a DLL-free deserializer that can operate over a multi-octave frequency range, which is compatible with the TIA/EIA-644 LVDS standard. The serializer in the SerDes receives 21 bits of parallel data (from the digital system) at a bit rate up to 80 Mbps, serializes it to (up to) 560 Mbps into three channels, along with a 1/7th rate clock signal. The deserializer uses these signals for recovering the original bit-stream. The chip has been designed in SCL 180nm CMOS technology, using high-voltage devices, for backward compatibility with the system using 3.3V supply. The worst case power consumption (obtained from post layout simulations) is 173.25mW and 207.6mW for the serializer and the deserializer designs, respectively, which indicates a very significant improvement with respect to the available products.
一个多倍频程范围SerDes与DLL免费接收器
高速串行链路中的反序列化器通常使用延迟锁定环(DLL)或锁相环(PLL)进行相位校准和数据信号采样。然而,这样的dll或pll具有有限的工作频率范围。在这个体系结构中,我们提出了一个可以在多倍频程频率范围内工作的无dll反序列化器,该反序列化器与TIA/EIA-644 LVDS标准兼容。SerDes中的串行器以高达80mbps的比特率接收21位并行数据(来自数字系统),将其串行到(高达)560mbps到三个通道,以及1/7速率时钟信号。反序列化器使用这些信号来恢复原始的比特流。该芯片采用SCL 180nm CMOS技术设计,采用高压器件,向后兼容3.3V电源系统。最坏情况下的功耗(从布局后的模拟中获得)分别为序列化器和反序列化器设计的173.25mW和207.6mW,这表明相对于现有产品有了非常显著的改进。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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