R. Thukral, Mohit Goswami, Sharayu Jagtap, Sandeep Goyal, Shalabh Gupta
{"title":"A Multi-Octave Frequency Range SerDes with a DLL Free Receiver","authors":"R. Thukral, Mohit Goswami, Sharayu Jagtap, Sandeep Goyal, Shalabh Gupta","doi":"10.1109/VDAT53777.2021.9600917","DOIUrl":null,"url":null,"abstract":"A deserializer in a high-speed serial link typically uses a delay-locked loop (DLL) or a phase-locked loop (PLL) for phase alignment and sampling of the data signal. However, such DLLs or PLLs have a limited operating frequency range. In this architecture, we have proposed a DLL-free deserializer that can operate over a multi-octave frequency range, which is compatible with the TIA/EIA-644 LVDS standard. The serializer in the SerDes receives 21 bits of parallel data (from the digital system) at a bit rate up to 80 Mbps, serializes it to (up to) 560 Mbps into three channels, along with a 1/7th rate clock signal. The deserializer uses these signals for recovering the original bit-stream. The chip has been designed in SCL 180nm CMOS technology, using high-voltage devices, for backward compatibility with the system using 3.3V supply. The worst case power consumption (obtained from post layout simulations) is 173.25mW and 207.6mW for the serializer and the deserializer designs, respectively, which indicates a very significant improvement with respect to the available products.","PeriodicalId":122393,"journal":{"name":"2021 25th International Symposium on VLSI Design and Test (VDAT)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 25th International Symposium on VLSI Design and Test (VDAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VDAT53777.2021.9600917","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A deserializer in a high-speed serial link typically uses a delay-locked loop (DLL) or a phase-locked loop (PLL) for phase alignment and sampling of the data signal. However, such DLLs or PLLs have a limited operating frequency range. In this architecture, we have proposed a DLL-free deserializer that can operate over a multi-octave frequency range, which is compatible with the TIA/EIA-644 LVDS standard. The serializer in the SerDes receives 21 bits of parallel data (from the digital system) at a bit rate up to 80 Mbps, serializes it to (up to) 560 Mbps into three channels, along with a 1/7th rate clock signal. The deserializer uses these signals for recovering the original bit-stream. The chip has been designed in SCL 180nm CMOS technology, using high-voltage devices, for backward compatibility with the system using 3.3V supply. The worst case power consumption (obtained from post layout simulations) is 173.25mW and 207.6mW for the serializer and the deserializer designs, respectively, which indicates a very significant improvement with respect to the available products.