Analysis of Standard Cells performance for In0.53Ga0.47As FinFET with underlap fin length for High Speed Applications

Abstract

In current CMOS technology for high-speed applications at the sub-14 nm technology node using In0.53Ga0.47As FinFETs is becoming a promising choice because of its exceptional electrical properties. The approach of improving FinFET standard cells utilizing In0.53Ga0.47As nFinFETs is suggested to offer a platform in advanced VLSI digital system flow occupying various standard cells. Gate-source/drain (G-S/D) underlap fin length (Lun) structures are effectively used to reduce the short channel effects for a long time. In this work, the implementation of various standard cells with different Lun in In0.53Ga0.47As nFinFETs to understand its significance. The device reliability was tested in the proposed work by varying the process variation on the height of fin, gate oxide thickness, and channel length offset parameter. Simulation results performed on the different standard cells with Lun= 3 nm method indicate the minimum delay by 42.26%.