基于FPGA的分布式数据采集系统的软硬件协同设计方法

A. Krishnan, M. H. Supriya, N. Sivanandan
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引用次数: 0

摘要

数据采集系统需要调节来自各种传感器的低水平模拟信号,并将其转换为数字格式,以便于下游处理。分布式DAQ系统是声纳系统中常用的一种系统,因为大型平台中使用了大量的声传感器,并且传感器是物理分布的。由分布式数据采集系统收集的数据实时传输到中央处理系统,在中央处理系统中对数据进行进一步处理。水下系统的运行环境对DAQ系统的设计有很大的限制。本文提出了一种基于硬件软件协同设计的方法来实现一个资源高效的基于fpga的分布式数据采集系统。在这里,通过以太网的确定性数据传输的功能是使用RTL模块实现的,远程健康监测和配置控制功能具有TCP/IP堆栈支持,是在FPGA内部的软处理器中实现的。为了减少外部电缆的数量和FPGA的资源利用率,处理器和RTL模块之间使用AXI交换机共享一个以太网MAC。在分布式数据采集系统中,传感器的同步采样是一个重要的要求。本文通过在FPGA上实现IEEE1588精确时间协议实现同步。通过在RGMII接口上实现PTP报文的时间戳,实现了接近300ns的同步精度。该实现是在Xilinx的Artix7 FPGA上完成的,资源利用率为36K lut和43K触发器。MicroBlaze软处理器使用100 MHz时钟,同步定时器使用200 MHz时钟生成。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Hardware-Software Co-design based Approach for Development of a Distributed DAQ System using FPGA
Data acquisition systems are required to condition the low-level analog signals from various sensors and to convert them into digital format in order to facilitate downstream processing. Distributed DAQ systems are commonly used in SONAR systems, as a large number of acoustic sensors are used in big platforms and the sensors are physically distributed. The data collected by the distributed DAQ systems are transmitted to a central processing system in real-time where further processing of the data is done. The operating environment of the underwater system can impose severe restrictions on the design of the DAQ system. This paper presents a hardware-software co-design based approach to implementing a resource-efficient FPGA-based distributed DAQ system. Here, the functionality of deterministic data transmission through Ethernet is implemented using RTL modules, and remote health monitoring and configuration control functionalities with TCP/IP stack support are implemented in a soft-processor inside FPGA. To reduce the number of external cables and the FPGA resource utilization, a single Ethernet MAC is shared between processor and RTL modules using AXI switches. Synchronized sampling of sensors is an important requirement in distributed DAQ systems. In this paper, synchronization is achieved by implementing the IEEE1588 precision time protocol in FPGA. By implementing the timestamping of the PTP messages at the RGMII interface, synchronization accuracy close to 300ns was achieved. The implementation was done on Artix7 FPGA from Xilinx with a resource utilization of 36K LUTs and 43K flip-flops. MicroBlaze soft-processor was used with 100 MHz clock and the Synchronization Timer was generated using a 200 MHz clock.
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