Formal Verification and Analysis of a Pseudo Random Number Generator

Formal verification and analysis of a crypto hardware requires a formal specification, formal proof of equivalence of the specification with the hardware realization. Pseudo Random Number Generator hardware in Verilog RTL or equivalent has an entropy source for random seed, crypto algorithms and processing unit, authenticated access depicting static behavior; and dynamic finite state machines (FSM) for data flow control, fault/error checks and recovery. This paper focusses on a unified, transitive, compositional formal verification and analysis of a FPGA based PRNG with statistical methods, quantitative physical measurements based analysis, symbolic logical equivalence and model checks, and properties verification.