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2007 7th International Conference on ASIC最新文献

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Array and high voltage path design for SONOS flash memory SONOS闪存阵列及高压路径设计
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415809
Dong Wu, L. Pan, Lei Sun, Jun Zhu
{"title":"Array and high voltage path design for SONOS flash memory","authors":"Dong Wu, L. Pan, Lei Sun, Jun Zhu","doi":"10.1109/ICASIC.2007.4415809","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415809","url":null,"abstract":"A 1.8 V/3.3 V 4 Mb Embedded SONOS flash memory has been successfully developed and verified with a 0.18 mum CMOS logic compatible integrated technology, in which a reverse read array architecture and a novel decoder circuit are proposed to improve the read speed and to reduce the chip area. Moreover, a high voltage path is also introduced to improve the stability and reliability of the system. The test results show that the high voltage path timing is correct, and that the chip area and the read speed are 4.4 mm2 and 17 ns, respectively.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114259332","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Behavioral model of data acquisition system by using Simulink 利用Simulink建立数据采集系统的行为模型
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415868
Shaoshi Yan, Xi Tian, Xin Zhao, Peng Li
{"title":"Behavioral model of data acquisition system by using Simulink","authors":"Shaoshi Yan, Xi Tian, Xin Zhao, Peng Li","doi":"10.1109/ICASIC.2007.4415868","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415868","url":null,"abstract":"A 4-channel parallel data acquisition system(DAS) has been advanced. In order to evaluate the performance of the DAS, the behavioral models of the basic blocks which constitute the DAS were founded to estimate the relationship between the blocks and the whole DAS. The Matlab/Simulink environment was employed to model and simulate the blocks.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122661871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An MBOK-UWB SoC transceiver in 0.181μm CMOS technology 基于0.181μm CMOS技术的MBOK-UWB SoC收发器
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415759
Shenmin Zhang, Jianliang Zhang, Mengmeng Liu, Shuo Wang, Liang Heng, R. Zhou
{"title":"An MBOK-UWB SoC transceiver in 0.181μm CMOS technology","authors":"Shenmin Zhang, Jianliang Zhang, Mengmeng Liu, Shuo Wang, Liang Heng, R. Zhou","doi":"10.1109/ICASIC.2007.4415759","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415759","url":null,"abstract":"A system-on-a-chip (SoC) pulse-based MBOK-UWB transceiver for high-speed wireless transmission is presented in this paper. The system achieves the data rate of 100 Mbps. The digital baseband implements RAKE receiving architecture, with M-ary bi-orthogonal keying (MB OK) spread spectrum modulation, low-density parity-check (LDPC) error-correct coding and Ethernet interface. The front-end circuits include low-power pulse generator, 3~5GHz wideband low-noise amplifier (LNA) and 1 Gsps 4 bit flash analog-to-digital converter (ADC). These modules of proposed SoC has been designed and fabricated in HJTC 0.18 mum 1P6M CMOS technology. The baseband had been designed and implemented in one Xilinx FPGA.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131161613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
ESD and latchup: Computer aided design (CAD) tools and methodologies for today and future VLSI designs ESD和闭锁:计算机辅助设计(CAD)工具和方法为今天和未来的超大规模集成电路设计
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415645
S. Voldman
{"title":"ESD and latchup: Computer aided design (CAD) tools and methodologies for today and future VLSI designs","authors":"S. Voldman","doi":"10.1109/ICASIC.2007.4415645","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415645","url":null,"abstract":"In summary, new methods for ESD and latchup analysis are being utilized to address today's technical problems in products, and design tools. As semiconductor tool and product complexity increases, future concepts are needed to address system on chip integration problems.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131291653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 6-digit RSD analog-to-quaternary converter with CMOS Current Mode Quaternary Adders 带CMOS电流模式四元加法器的6位RSD模拟-四元转换器
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415623
C. Chan, C. Chan, C. Choy, K. Pun
{"title":"A 6-digit RSD analog-to-quaternary converter with CMOS Current Mode Quaternary Adders","authors":"C. Chan, C. Chan, C. Choy, K. Pun","doi":"10.1109/ICASIC.2007.4415623","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415623","url":null,"abstract":"This paper presents a 6-digit Analog-to-Quaternary Converter (AQC) using a 0.35 mum CMOS process. The proposed CMOS AQC uses pipelined architecture with redundant signed digit (RSD) error correction algorithm. A CMOS quaternary adder is proposed to handle quaternary addition in the correction algorithm. The converter has simulated SNDR SFDR and THD of 65.17 dB, 73.89d B and -73.26 dB at 2.5V supply voltage and 50 MHz sampling rate.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131512397","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Implementation of fast Huffman decoding algorithm 实现快速霍夫曼解码算法
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415744
Ya-Jun He, Duoli Zhang, Bin Shen, Luofeng Geng
{"title":"Implementation of fast Huffman decoding algorithm","authors":"Ya-Jun He, Duoli Zhang, Bin Shen, Luofeng Geng","doi":"10.1109/ICASIC.2007.4415744","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415744","url":null,"abstract":"An efficient Huffman decoding method is presented in this paper. This new method first partitions a Huffman tree into subtrees. Then some look-up tables are used to represent these subtrees and the symbols of some subtrees are decoded by direct combinational logic. It is shown that by employing this technique decoding operations become significantly faster, and the memory consumption also becomes much smaller compared to the normal Huffman decoding.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128014102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Leakage aware design for next generation’s SOCs 下一代soc的泄漏感知设计
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415883
R. Zafalon
{"title":"Leakage aware design for next generation’s SOCs","authors":"R. Zafalon","doi":"10.1109/ICASIC.2007.4415883","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415883","url":null,"abstract":"We describe basic design techniques, that have proven to hold great potential for leakage optimization in practical design environments. They range from gate/circuit level (e.g. dual Vth, MTCMOS, sleep transistor insertion), to memory blocks (e.g. array partitioning, sub-banking, bit line splitting, cache decay, drowsy state memory, exploit locality, etc) and architectural styles (e.g. region-based adaptive Vdd and Body Biasing, Vth hopping, Power gating, etc.). A selection of significative industrial solutions obtained by the application of low-power techniques to proprietary designs covering different application domains (including high-performance microprocessors, memory/cache structure and hardware platforms for embedded multi-media processing) will be reported as well.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133690029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A fractional-N frequency synthesizer with a wide-band small gain-Fluctuation VCO for mobile DTV applications 用于移动数字电视应用的带宽带小增益波动压控振荡器的分数n频率合成器
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415627
T. Ahn, Je-cheol Moon, Yong Moon
{"title":"A fractional-N frequency synthesizer with a wide-band small gain-Fluctuation VCO for mobile DTV applications","authors":"T. Ahn, Je-cheol Moon, Yong Moon","doi":"10.1109/ICASIC.2007.4415627","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415627","url":null,"abstract":"A fully integrated Sigma-Delta fractional-N frequency synthesizer featuring wide-band and small VCO-gain (KVCO) fluctuation is presented. To cover wide-band frequency operation for mobile DTV applications, 6-bit switched-capacitor bank LC VCO is used, and for small KVCO fluctuation, four self-controlled varactor blocks are added to conventional capacitor bank scheme. The integrated VCO tuning range is as wide as 890 MHz (65%) from 910 MHz to 1.8 GHz, which can cover all the desired frequencies for the DVB-H/ISDB-T/T-DMB receiver and achieves 52% smaller KVCO fluctuation than that of a conventional design.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"321 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132349861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Parametric analysis of multiple interconnects via canonical reduced order modeling 基于规范降阶建模的多互连参数分析
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415833
Zhigang Hao, G. Shi
{"title":"Parametric analysis of multiple interconnects via canonical reduced order modeling","authors":"Zhigang Hao, G. Shi","doi":"10.1109/ICASIC.2007.4415833","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415833","url":null,"abstract":"For design nodes at 65 nm and below, timing will essentially be a statistical measure of the fabricated circuit and heavily correlated with process variation. This paper proposes a novel parametric interconnect analysis using canonical reduced order modeling. Models in canonical forms have the feature of a small number of free model parameters. This property can be made use of effectively for parametric analysis via interpolation. Experimental results demonstrate the effectiveness of the proposed methodology.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133392870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improved digital calibration technology in a 12-b, 40-MS/s pipelined ADC 改进了12 b 40 ms /s流水线ADC的数字校准技术
2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI: 10.1109/ICASIC.2007.4415617
Huayu Jia, Guican Chen, Jun Cheng, Kai Zhang, Lei Shen
{"title":"Improved digital calibration technology in a 12-b, 40-MS/s pipelined ADC","authors":"Huayu Jia, Guican Chen, Jun Cheng, Kai Zhang, Lei Shen","doi":"10.1109/ICASIC.2007.4415617","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415617","url":null,"abstract":"In the design of 12-bits 40MSample/s pipelined ADC, the traditional close-loop high performance residue amplifier in first stage is replaced by an open-loop amplifier to reduce power dissipation and increase circuit speed. The errors brought by open-loop amplifier are evaluated and calibrated by an improved statistics-based background calibration technology. A self-adaptive search algorithm and a magnitude incremental comparison algorithm are presented in statistics-based background calibration technology to improve residue difference estimator circuit and LUT (look up table) of binary monotonically function respectively. The improved calibration technology can reduce digital circuit power dissipation and size significantly. Simulation results show that power consumption of digital circuit is reduced by 93% and room of ROM is saved by 84%. The ADC is implemented in SMIC 0.18 CMOS process, consumes 210 mW, and has a layout size of 3.2*3.7 mm2.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134086034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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