Array and high voltage path design for SONOS flash memory

Abstract

A 1.8 V/3.3 V 4 Mb Embedded SONOS flash memory has been successfully developed and verified with a 0.18 mum CMOS logic compatible integrated technology, in which a reverse read array architecture and a novel decoder circuit are proposed to improve the read speed and to reduce the chip area. Moreover, a high voltage path is also introduced to improve the stability and reliability of the system. The test results show that the high voltage path timing is correct, and that the chip area and the read speed are 4.4 mm2 and 17 ns, respectively.