2007 7th International Conference on ASIC最新文献

{"title":"Leakage power reduction through dual Vth assignment considering threshold voltage variation","authors":"Yu Wang, Xukai Shen, Rong Luo, Huazhong Yang","doi":"10.1142/S0218126609005642","DOIUrl":"https://doi.org/10.1142/S0218126609005642","url":null,"abstract":"In today's sub-100nm CMOS technologies, leakage current has become an important part of the total power consumption, affecting both yields and lifetime of digital circuits. Dual Vth assignment, which is proven to be an effective method of reducing leakage power in the past, is also effective in today's technologies with certain modifications. In the paper, based on a statistical timing analysis (SSTA) framework we presented a dual Vth assignment method which can effectively reduce the leakage power even in the presence of large Vth variation. Besides, we use a statistical DAG pruning method which takes correlation between gates into account to speed up the dual Vth assignment algorithm. Experimental results show that statistical dual Vth assignment can reduce on average 40% more leakage current compared with conventional static method without affecting the performance constraints. Our DAG pruning method can reduce on average 30% gates in the circuit and save up to 50% of the total run time.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"357 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132895819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Software defined cognitive radios","authors":"R. Harjani, A. Tewfik, G. Sobelman","doi":"10.1109/ICASIC.2007.4415555","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415555","url":null,"abstract":"The wide proliferation of wireless services and applications with increasing bandwidth needs is rapidly creating a spectrum shortage. However, the problem is caused primarily by inefficient legacy spectrum allocation policies, so that even when some applications suffer from lack of bandwidth, there is idle capacity in other bands. To deal with this challenge, the FCC, ITU and other regulatory organizations have begun to explore an open spectrum policy implemented by programmable wireless networks. Such wireless networks use cognitive, software reconfigurable radios to increase the efficiency of spectrum access. In particular such programmable wireless networks maximize the availability and enhance the quality of service of diverse applications using the most appropriate access network, or an aggregation of such networks, for any given local conditions. A software defined radio (SDR) terminal is essentially a reconfigurable system that can be dynamically programmed in software to reconfigure the characteristics of the hardware through the use of clearly defined APIs residing on top of a flexible hardware layer. The SDRs use different types of hardware to accomplish various communication tasks. In addition to the grammability and flexibility provided by the DSPs and software-driven communication parameters such as modulation, medium access, cryptography, etc, software defined radios also provide field service capability. So, when requirements change, code downloads, upgrades and modifications are relatively easy to execute. Ultimately, the success of the programmable wireless network vision will hinge on its ability to meet the high level needs of users, service providers, network operators and hardware and software developers. Ubiquitous access to applications with proper quality levels, low cost services, user friendliness, fast and open service creation, lifetime and flexibility of equipment, common execution environment, fast product design and manufacturing, to mention a few, translate into well defined technology requirements. In this tutorial we will discuss system, circuit and implementation issues necessary to design a programmable wireless network that meets these requirements.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131509454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multi-level signaling for energy-efficient on-chip interconnects","authors":"F. Rokhani, G. Sobelman","doi":"10.1109/ICASIC.2007.4415572","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415572","url":null,"abstract":"In this paper, we develop multi-level signaling schemes for on-chip interconnects in order to achieve energy-efficient communication. The methodology uses both bus multiplexing and low-swing signaling characteristics, while keeping the total bus area fixed. A physics-based energy model for coupling capacitance is developed which accurately captures the energy consumption of very deep sub-micron (VDSM) on-chip interconnect in the context of multi-level signals. Results show that our proposed bus achieves energy savings for intermediate-layer interconnect lines of as much as 76% compared to binary signaling. In addition, wire bandwidth is improved by up to 16% compared to prior approaches.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134478380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An efficient transformation method for DFRM expansions","authors":"H. Xu, M. Yang, L. Wang, J. Tong, A. Almaini","doi":"10.1109/ICASIC.2007.4415839","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415839","url":null,"abstract":"Dual Form of Reed-Muller (DFRM) expansions with fixed polarity are derived from Reed-Muller (RM) expansions by using the operation of Kronecker matrix products. An efficient decomposition method is proposed based on the formulation. The method can be used for the transformation between from DFRM expansions to RM expansions within the same fixed polarity as well. Hence, the proposed method is bidirectional. After decomposition, the calculation of the duplicated matrix is avoided, resulting in less computation time. Time complexity of the algorithm is 0(21.5n). The time used for small variables is virtual zero for the tested MCNC benchmarks. For large variable, it still works very well and achieves less than 20 seconds for 25-variable benchmark. In the implementation, only on-set coefficients are used. Consequently, the space complexity is O(M), where M is the number of on-set coefficients. It makes simultaneous optimization in both RM and DFRM expansions possible.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"58 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122393872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel compact soft-start circuit with internal circuitry for DC-DC converters","authors":"Yuan Bing, Lai Xin-quan, Ye Qiang, Jia Xinzhang","doi":"10.1109/ICASIC.2007.4415664","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415664","url":null,"abstract":"A novel internal soft-start circuit with simple topology for DC-DC buck converters is presented. It is implemented by controlling the output of error amplifier to make switch current limit increases in steps without using external capacitor, which reduces the component cost, saves board space and benefits for portable applications. This circuit is designed on the basis of Hynix 0.5 mum CMOS process, and its performance has been verified by Hspice simulation and measurement results. Avoiding the inrush current and overshoot vloltage, the IC starts up in 4 steps in 1.6 ms with input voltage of 3.6 V, output voltage of 1.8 V, output capacitor of 22 muF and load current of 1.1 A.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"443 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115274631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A modified golumbic algorithm for permutation graphs in VLSI","authors":"Xiaodi Huang, G. Wang","doi":"10.1109/ICASIC.2007.4415611","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415611","url":null,"abstract":"In this paper, a modified Golumbic algorithm is presented to find the maximum set in a permutation graphs. The modified algorithm runs in O(n log n) times like the original algorithm[1], but some step timing O(n) in original algorithm is cut in the proposed method, then time consumption for solution is decreased by the modification. The example shows the anticipative result.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116679592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A partial scramble scheme for H.264 video","authors":"Jidong Wang, Y. Fan, T. Ikenaga, S. Goto","doi":"10.1109/ICASIC.2007.4415752","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415752","url":null,"abstract":"There are many encryption algorithms for general data such as text data. But they are unsuitable for the encryption of the video data because of the real time constraint of the video applications. In this paper, a partial scramble scheme is proposed. The main feature of this scheme is making use of the characteristics of a H.264/AVC video. Instead of encrypting all the video data, some important parameters of the H.264/AVC video such as motion vector difference (MVD) and trailing ones (Tl) of CAVLC module are scrambled in this scheme. There are 3 scramble levels in this scheme. For different scramble levels, MVDs and Tls of different MBs in a frame are scrambled according to different part of the key stream generated by a stream cipher. The advantage of this scheme is that it adds very small computational overhead to H.264/AVC coding process. Hence it is fast enough to be used for real time video applications. This scheme can be utilized in mobile and entertainment applications.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121025338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The cycle accurate DSP model design based on SystemC","authors":"Lin Dai, Zhenyao Liu","doi":"10.1109/ICASIC.2007.4415850","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415850","url":null,"abstract":"With the development of the DSP design technique, the DSP structure becomes more and more complex and the speed of RTL simulation is slower and slower. In this paper, a cycle accurate DSP model based on SystemC is designed to speed up the simulation. Through the simulation of g.721 audio encoding program and the IDCT that is the main part of image processing, the time of cycle accurate DSP model simulation is about one minute and ten seconds, however the time of RTL simulation is about thirty minutes and five minutes.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121052489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 20mW 200MHz CMOS continuous-time sigma-delta modulator with 5MHz signal bandwidth and 12 bits of resolution","authors":"Yi-ran Li, Jian-qiu Chen, Jun Xu, Junyan Ren","doi":"10.1109/ICASIC.2007.4415727","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415727","url":null,"abstract":"A continuous-time sigma-delta modulator with 12 bits of resolution over a signal bandwidth of 5 MHz is presented. The simulation results show that it consumes 20 mW from a 1.8 V power supply, utilizing SMIC 0.18-um CMOS process.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"252 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121100307","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Stochastic based extended krylov subspace method for power/ground network analysis","authors":"Xiaolong Yuan, J. Fan, Bao Liu, S.X.-D. Tan","doi":"10.1109/ICASIC.2007.4415825","DOIUrl":"https://doi.org/10.1109/ICASIC.2007.4415825","url":null,"abstract":"In this paper, we present a novel stochastic simulation approach based on extended Krylov subspace method for on-chip power grid analysis. The new method performs the analysis by using random walk in a stochastic manner. But different from the existing random walk method, the moments of the circuits are computed and extended Krylov subspace (EKS) method is used to calculate the responses in frequency domain. The new method can compute the transient responses in a local manner, which is in contrast to the existing random walk method, thus improves the existing frequency-domain random walk method by using extended Krylov subspace method. The resulting method is more numerically stable and faster than existing random walk methods. Experimental results demonstrate the advantages of the proposed method, called rwEKS, over EKS method for localized power grid analysis.","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127099019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}